Abstract: Techniques for performing an unconditional jump are described. In some examples, an instruction is processed to perform the unconditional jump. In some examples, the instruction is to at least include one or more fields for an opcode and a 64-bit bit immediate, wherein the 64-bit immediate is to encode an absolute address and the opcode is to indicate execution circuitry is jump to the absolute address.

Abstract: In an embodiment, a processor for redirecting requests includes a processing engine to execute a guest system, and monitoring circuitry coupled to the processing engine. The monitoring circuitry may be to: receive, from the guest system, a first request to access a first virtual counter; in response to a receipt of the first request, determine, based a mapping register of the processor, a first physical counter mapped to the first virtual counter; and redirect the first request to the first physical counter mapped to the first virtual counter. Other embodiments are described and claimed.

Abstract: An apparatus and method for booting a processor directly into a paged 64-bit execution environment. For example, one embodiment of an a processor comprises: a register to store a first value and a second value related to a secure boot process; a plurality of cores, at least one of which performs operations comprising: receiving a first initialization message, the core to clear a plurality of registers responsively; receiving a second initialization message and reading the first and second values responsively, the first value indicating whether a first initialization mode is supported, and the second value comprising an address pointer identifying a data structure comprising a plurality of state values; and initializing a paged 64-bit execution environment using the state values from the data structure responsive to the first value indicating the first initialization mode is supported and the data structure indicating enabling the paged 64-bit execution environment.

Abstract: An apparatus and method for a more efficient system management mode. For example, one embodiment of a processor comprises: a plurality of cores, at least a first core of the plurality of cores to perform operations to cause the plurality of cores to enter into a system management mode (SMM), the operations comprising: allocating a memory region for a system management RAM (SMRAM); writing an SMRAM state save location to a first register; and generating a page table in the SMRAM, including mapping a virtual address space a physical address space.

Abstract: An apparatus and method are described for reduced power TLB management. For example, one embodiment of a processor comprises: a plurality of cores; a first core of the plurality of cores comprising: a first translation lookaside buffer (TLB) to store address translations associated with page table walk operations, and power management logic to cause the first core to enter into a first low power state in which the address translations in the first TLB are no longer valid, wherein prior to entering into the low power state, the first core is to write an indication in a memory location that the first TLB no longer contains valid address translations; a second core of the plurality of cores to perform an operation requiring invalidation of one or more of the address translations previously stored in the first TLB, the second core to determine whether to transmit a request to the first core to invalidate the one or more address translations based on the indication.

Abstract: An apparatus and method for implementing a new virtualized execution environment while supporting instructions and operations of a legacy virtualized execution environment.

Abstract: An apparatus and method for switching between different types of paging using separate control registers and without disabling paging. For example, one embodiment of a processor comprises: a first control register to store a first base address of a first paging structure associated with a first type of paging having a first number of paging structure levels; a second control register to store a second base address of a second paging structure associated with a first type of paging having a second number of paging structure levels greater than the first number of paging structure levels; page walk circuitry to select either the first base address from the first control register or the second base address from the second control register responsive to a first address translation request, the selection based on a characteristic of program code initiating the address translation request.

Abstract: Techniques and mechanisms for a processor to determine an operational mode based on metadata for a page table. In an embodiment, an instruction fetch unit of the processor detects a pointer to a next instruction, in a sequence of instructions, which is to be prepared for execution with a core of the processor. Based on the pointer, a page table is identified as including an entry which indicates a location of the instruction. The page table includes, or otherwise corresponds to, metadata which comprises an identifier of an operational mode of the processor. Based on the metadata, the processor is transitioned to the operational mode in preparation for an execution of the instruction. In another embodiment, the operational mode is one of multiple operational modes which each correspond to a different instruction set architecture.

Abstract: Techniques for CPUID are described. In some examples, a CPUID instruction is to include at least one field for an opcode, the opcode to indicate execution circuitry is to return processor identification and feature information determined by input into a first register and a second register, wherein the processor identification and feature information is to include an indication of an availability of a second execution mode that at least deprecates features of a first execution.

Abstract: Techniques for using CPUID for showing features that are deprecated are described. In some examples, CPUID is to include at least one field for an opcode, one or more fields to identify a source operand which is to store a LSL selector value, and one or more fields to identify a destination register operand, wherein the opcode is to indicate that execution circuitry is to, when the single instruction has been enabled by a setting of a bit in a control register, write a LSL value stored in the control register to the destination operand when the LSL selector value of the first source register operand matches a LSL selector value stored in the control register, and set a flag in a flags register.

Abstract: Techniques for supporting a far jump and IRET are described. An example far jump instruction support includes support for a single instruction to include at least one field for an opcode and one or more fields for an operand, wherein the opcode is to indicate execution circuitry is to perform a far jump and the operand is to specify an address to be jumped to, wherein an operand size attribute of the instance of the instruction is 32-bit or greater and the instruction has been enabled by a setting of a bit in a compatibility control register.

Abstract: Techniques relating to virtual idle loops are described. In an embodiment, decoder circuitry decodes a single instruction. The single instruction includes a field for an identifier of a first source operand, a field for an identifier of a second source operand, a field for an identifier of a destination operand, and a field for an opcode. Execution circuitry executes the decoded instruction according to the opcode to: write the first source operand to a memory location identified by the second source operand; compute an index into a control array based at least in part on the destination operand; and determine whether to exit to a hypervisor of a Virtual Machine (VM) based at least in part on data stored at a location in the control array, wherein the location is to be identified by the computed index. Other embodiments are also disclosed and claimed.

Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

Abstract: In an embodiment, a processor for redirecting requests includes a processing engine to execute a guest system, and monitoring circuitry coupled to the processing engine. The monitoring circuitry may be to: receive, from the guest system, a first request to access a first virtual counter; in response to a receipt of the first request, determine, based a mapping register of the processor, a first physical counter mapped to the first virtual counter; and redirect the first request to the first physical counter mapped to the first virtual counter. Other embodiments are described and claimed.

Abstract: Techniques for an instruction for a Runtime Call operation are described. An example apparatus comprises decoder circuitry to decode a single instruction, the single instruction to include a field for an identifier of an opcode, the opcode to indicate execution circuitry is to execute a no operation when a runtime call destination equals a predetermined value; and execute an indirect call with the runtime call destination as a destination address when the runtime call destination does not equal the predetermined value. Other examples are described and claimed.

Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

Abstract: Techniques and mechanisms for configuring processor event-based sampling (PEBS) with a set of control registers. In an embodiment, a first control register of a processor is programmed to store a physical address of a location in a buffer which receives PEBS records. The first control register is further programmed or otherwise configured to store an indication of a size of the buffer. A second control register of the processor stores a physical address of a location in the buffer were a next PEBS record is to be stored. In another embodiment, the processor further comprises multiple control registers which variously configure PEBS generation on a per-counter basis.

Abstract: Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.

Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

Abstract: A processor includes a counter to store a cycle count that tracks a number of cycles between retirement of a first branch instruction and retirement of a second branch instruction during execution of a set of instructions. The processor further includes a stack of registers coupled to the counter, wherein the stack of registers is to store branch type information including: a first value of the counter when the first branch instruction is retired; a second value of the counter when the second branch instruction is retired; a first type information value indicating a type of the first branch instruction; and a second type information value indicating a type of the second branch instruction.