Patents by Inventor Andreas Olsson
Andreas Olsson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240129370Abstract: A user interface arrangement comprising a controller, a sensor and a communication interface, wherein the sensor is arranged to receive input, and the controller is configured to: cause the user interface arrangement to operate in a first power level; receive the input; detect an indication of at least one command, and in response thereto cause the user interface arrangement to operate in a second power level, wherein the second power level is higher than the first power level; determine that at least one IoT device is in front of the user interface arrangement, and in response thereto cause the user interface arrangement to operate in a second power level, wherein the third power level is higher than the second power level; extract at least one command from the input; match the extracted at least one command to the at least one IoT device, and if a match is found; execute the extracted at least one command on the matching IoT device.Type: ApplicationFiled: March 3, 2021Publication date: April 18, 2024Inventors: Fredrik Dahlgren, Alexander Hunt, Andreas Kristensson, Magnus Olsson
-
Patent number: 11955972Abstract: There is provided a field-programmable gate array, FPGA, device (100) comprising a configurable logic block, CLB, (110) comprising a logic inverter (120) comprising a high-electron-mobility transistor, HEMT, (130), wherein the HEMT comprises: a Si substrate (384); an AlyGay-1N layer structure (380), wherein 0<y?1; a GaN layer structure (382); and a crystal transition layer structure (386) arranged on the Si substrate. The crystal transition layer comprises: a plurality of vertical nanowire structures (388) perpendicularly arranged on the Si substrate, and an AlxGax-1N layer structure (389), wherein 0?x<1, wherein the AlxGax-1N layer structure is arranged to vertically and laterally enclose the vertical nanowire structures. There is also provided an AI processing system comprising said FPGA device (100).Type: GrantFiled: March 10, 2021Date of Patent: April 9, 2024Assignee: Epinovatech ABInventor: Martin Andreas Olsson
-
Publication number: 20230352575Abstract: There is provided a vertical high-electron-mobility transistor, HEMT (100), comprising: a drain contact (410), a nanowire layer (500) arranged on the drain contact (410) and comprising at least one vertical nanowire (510) and a supporting material (520) laterally enclosing the at least one vertical nanowire (510), a heterostructure (600) arranged on the nanowire layer and comprising an AIGaN-layer (610) and a GaN-layer (620) together forming a heterojunction, at least one source contact (420a, 420b) in contact with the heterostructure (600), and a gate contact (430) in contact with the heterostructure (600), arranged above the at least one vertical nanowire (510), wherein the at least one vertical nanowire (510) is forming an electron transport channel between the drain contact and the heterostructure. There is also provided a method for producing a vertical HEMT (100).Type: ApplicationFiled: May 27, 2021Publication date: November 2, 2023Inventor: Martin Andreas Olsson
-
Publication number: 20230327009Abstract: Apparatuses and methods relating to semiconductor layer structures are disclosed. A method for producing a semiconductor layer structure ay involve providing a Si substrate comprising a top surface, forming a first semiconductor layer on the substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures, arranged perpendicularly to the top surface of the substrate, the first semiconductor layer comprising AIN, and epitaxially growing a second semiconductor layer which laterally and vertically encloses the plurality of vertical nanowire structures thereby encapsulating dislocations in shells around the nanowires, wherein the second semiconductor layer comprises AlxGa1-xN, wherein 0:x:0.95.Type: ApplicationFiled: May 22, 2023Publication date: October 12, 2023Inventor: Martin Andreas Olsson
-
Publication number: 20230261621Abstract: There is provided a monolithic microwave integrated circuit, MMIC, front-end module which may include: a gallium nitride structure supported by a silicon substrate, a silicon-based transmit/receive switch having a transmit mode and a receive mode, a transmit amplifier configured to amplify an outgoing signal to be transmitted by said MMIC front-end module, wherein said transmit amplifier is electrically connected to said transmit/receive switch, wherein said transmit amplifier comprises a gallium nitride high-electron-mobility transistor, HEMT, formed in said gallium nitride structure. The MMIC front-end module may further include a receive amplifier configured to amplify an incoming signal received by said MMIC front-end module, wherein said receive amplifier is electrically connected to said transmit/receive switch, wherein said receive amplifier may include a gallium nitride HEMT formed in said gallium nitride structure.Type: ApplicationFiled: April 7, 2023Publication date: August 17, 2023Inventor: Martin Andreas Olsson
-
Patent number: 11695066Abstract: There is provided a semiconductor layer structure (100) comprising: a Si substrate (102) having a top surface (104); a first semiconductor layer (110) arranged on said substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures (112) arranged perpendicularly to said top surface of said substrate, the first semiconductor layer comprising AlN; a second semiconductor layer (120) arranged on said first semiconductor layer laterally and vertically enclosing said nanowire structures, the second semiconductor layer comprising AlxGa1-xN, wherein 0?x?0.95; a third semiconductor layer (130) arranged on said second semiconductor layer, the third semiconductor layer comprising AlyGa1-yN, wherein 0?y?0.95; and a fourth semiconductor layer (140) arranged on said third semiconductor layer, the fourth semiconductor layer comprising GaN. There is also provided a high-electron-mobility transistor device and methods of producing such structures and devices.Type: GrantFiled: June 10, 2022Date of Patent: July 4, 2023Assignee: Epinovatech ABInventor: Martin Andreas Olsson
-
Patent number: 11652454Abstract: There is provided a monolithic microwave integrated circuit, MMIC, front-end module (100) comprising: a gallium nitride structure (110) supported by a silicon substrate (120); a silicon-based transmit/receive switch (130) having a transmit mode and a receive mode; a transmit amplifier (112) configured to amplify an outgoing signal to be transmitted by said MMIC front-end module, wherein said transmit amplifier is electrically connected (132) to said transmit/receive switch, wherein said transmit amplifier comprises a gallium nitride high-electron-mobility transistor, HEMT, (114) formed in said gallium nitride structure; and a receive amplifier (113) configured to amplify an incoming signal received by said MMIC front-end module, wherein said receive amplifier is electrically connected (133) to said transmit/receive switch, wherein said receive amplifier comprises a gallium nitride HEMT (115) formed in said gallium nitride structure.Type: GrantFiled: June 17, 2022Date of Patent: May 16, 2023Assignee: EPINOVATECH ABInventor: Martin Andreas Olsson
-
Publication number: 20230146820Abstract: There is provided an induction machine (100) comprising a rotor (120); a stator (140); and a phase-shift oscillator (160). The stator comprises: a first winding (141); and a second winding (142), arranged at a first angle (101) relative to said first winding. The phase-shift oscillator comprises: a transistor (170), the transistor (170) being a high-electron mobility transistor, HEMT; and a phase-shift network (180). The first winding is connected to a first node (181) of the phase-shift network and wherein the second winding is connected to a second node (182) of the phase-shift network, wherein the phase-shift oscillator is configured to provide a first phase electric signal at the first node and a second phase electric signal at the second node, wherein a difference between the first and second phase corresponds to the first angle. There is also provided an electric aircraft propulsion system comprising the induction machine.Type: ApplicationFiled: May 5, 2021Publication date: May 11, 2023Inventor: Martin Andreas Olsson
-
Patent number: 11634824Abstract: A device for performing electrolysis of water is disclosed. The device may include a semiconductor structure with a surface and an electron guiding layer below said surface, the electron guiding layer of the semiconductor structure being configured to guide electron movement in a plane parallel to the surface. The electron guiding layer of the semiconductor structure may include an InGaN quantum well or a heterojunction, the heterojunction being a junction between AlN material and GaN material or between AlGaN material and GaN material and at least one metal cathode arranged on the surface of the semiconductor structure. The device may further include at least one photoanode arranged on the surface of the semiconductor structure, wherein the at least one photoanode may include a plurality of quantum dots of InxGa(1-x)N material, wherein 0.4?x?1. A system including such a device is also disclosed.Type: GrantFiled: June 8, 2022Date of Patent: April 25, 2023Assignee: Epinovatech ABInventor: Martin Andreas Olsson
-
Publication number: 20230119801Abstract: There is provided a field-programmable gate array, FPGA, device (100) comprising a configurable logic block, CLB, (110) comprising a logic inverter (120)comprising a high-electron-mobility transistor, HEMT, (130), wherein the HEMT comprises: a Si substrate (384); an AlyGay-1N layer structure (380), wherein 0<y?1; a GaN layer structure (382); and a crystal transition layer structure (386) arranged on the Si substrate. The crystal transition layer comprises: a plurality of vertical nanowire structures (388) perpendicularly arranged on the Si substrate, and an AlxGax-1N layer structure (389), wherein 0?x<1, wherein the AlxGax-1N layer structure is arranged to vertically and laterally enclose the vertical nanowire structures. There is also provided an Al processing system comprising said FPGA device (100).Type: ApplicationFiled: March 10, 2021Publication date: April 20, 2023Inventor: Martin Andreas Olsson
-
Publication number: 20220416025Abstract: A reinforced thin-film device is disclosed. The reinforced thin-film device comprising: a substrate having a top surface for supporting an epilayer; a mask layer patterned with a plurality of nanosize cavities disposed on said substrate to form a needle pad; a thin-film of, relative to the substrate, lattice-mismatched semiconductor disposed on said mask layer, wherein said thin-film comprises a plurality of in parallel spaced semiconductor needles of said lattice-mismatched semiconductor embedded in said thin-film, wherein said plurality of semiconductor needles are vertically disposed in the axial direction towards said substrate in said plurality of nanosize cavities of said mask layer; a, relative to the substrate, lattice-mismatched semiconductor epilayer provided on said thin-film and supported thereby; and a FinFET transistor arranged on the lattice-mismatched semiconductor epilayer.Type: ApplicationFiled: September 2, 2022Publication date: December 29, 2022Inventor: Martin Andreas Olsson
-
Publication number: 20220399826Abstract: There is provided an AC-DC converter circuit (100) for high power charging of an electrical battery. The circuit comprises an input rectifier comprising a first node and a second node. The input rectifier (110) is configured to receive an AC voltage at the first node (112) and provide a rectified voltage at the second node (114). The circuit further comprises a first transistor (120), comprising a first gate node (122), a first source node (124), and a first drain node (126). The first drain node is connected to the second node of the input rectifier. The first gate node is connected to a ground node (170). The circuit further comprises a second transistor (130), comprising a second gate node (132), a second source node (134), and a second drain node (136). The second drain node is connected to the first source node. The second transistor materially corresponds to the first transistor.Type: ApplicationFiled: October 22, 2020Publication date: December 15, 2022Inventor: Martin Andreas Olsson
-
Publication number: 20220396886Abstract: A device for performing electrolysis of water is disclosed. The device comprising: a semiconductor structure comprising a surface and an electron guiding layer below said surface, the electron guiding layer of the semiconductor structure being configured to guide electron movement in a plane parallel to the surface, the electron guiding layer of the semiconductor structure comprising an InGaN quantum well or a heterojunction, the heterojunction being a junction between AlN material and GaN material or between AlGaN material and GaN material; at least one metal cathode arranged on the surface of the semiconductor structure; and at least one photoanode arranged on the surface of the semiconductor structure, wherein the at least one photoanode comprises a plurality of quantum dots of InxGa(1?x)N material, wherein 0.4?x?1. A system comprising such device is also disclosed.Type: ApplicationFiled: June 8, 2022Publication date: December 15, 2022Inventor: Martin Andreas Olsson
-
Publication number: 20220393656Abstract: There is provided a monolithic microwave integrated circuit, MMIC, front-end module (100) comprising: a gallium nitride structure (110) supported by a silicon substrate (120); a silicon-based transmit/receive switch (130) having a transmit mode and a receive mode; a transmit amplifier (112) configured to amplify an outgoing signal to be transmitted by said MMIC front-end module, wherein said transmit amplifier is electrically connected (132) to said transmit/receive switch, wherein said transmit amplifier comprises a gallium nitride high-electron-mobility transistor, HEMT, (114) formed in said gallium nitride structure; and a receive amplifier (113) configured to amplify an incoming signal received by said MMIC front-end module, wherein said receive amplifier is electrically connected (133) to said transmit/receive switch, wherein said receive amplifier comprises a gallium nitride HEMT (115) formed in said gallium nitride structure.Type: ApplicationFiled: June 17, 2022Publication date: December 8, 2022Inventor: Martin Andreas Olsson
-
Patent number: 11469300Abstract: A reinforced thin-film device (100, 200, 500) including a substrate (101) having a top surface for supporting an epilayer; a mask layer (103) patterned with a plurality of nanosize cavities (102, 102?) disposed on said substrate (101) to form a needle pad; a thin-film (105) of lattice-mismatched semiconductor disposed on said mask layer (103), wherein said thin-film (105) comprises a plurality of in parallel spaced semiconductor needles (104, 204) of said lattice-mismatched semiconductor embedded in said thin-film (105), wherein said plurality of semiconductor needles (104, 204) are substantially vertically disposed in the axial direction toward said substrate (101) in said plurality of nanosize cavities (102, 102?) of said mask layer (103), and where a lattice-mismatched semiconductor epilayer (106) is provided on said thin-film supported thereby.Type: GrantFiled: April 23, 2019Date of Patent: October 11, 2022Assignee: Epinovatech ABInventor: Martin Andreas Olsson
-
Publication number: 20220302293Abstract: There is provided a semiconductor layer structure (100) comprising: a Si substrate (102) having a top surface (104); a first semiconductor layer (110) arranged on said substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures (112) arranged perpendicularly to said top surface of said substrate, the first semiconductor layer comprising AlN; a second semiconductor layer (120) arranged on said first semiconductor layer laterally and vertically enclosing said nanowire structures, the second semiconductor layer comprising AlxGa1-xN, wherein 0?x?0.95; a third semiconductor layer (130) arranged on said second semiconductor layer, the third semiconductor layer comprising AlyGa1-yN, wherein 0?y?0.95; and a fourth semiconductor layer (140) arranged on said third semiconductor layer, the fourth semiconductor layer comprising GaN. There is also provided a high-electron-mobility transistor device and methods of producing such structures and devices.Type: ApplicationFiled: June 10, 2022Publication date: September 22, 2022Inventor: Martin Andreas Olsson
-
Publication number: 20220231298Abstract: This disclosure is directed toward a method for producing a solid-state battery layer structure. The method may include providing an anode layer comprising silicon, forming a plurality of nanowire structures including silicon and/or gallium nitride on the anode layer and depositing a solid electrolyte layer on the anode layer. In some examples, the method may also include depositing a cathode layer on the solid electrolyte layer, depositing a cathode current collector metal layer on the cathode layer, etching holes through the anode layer, filling the holes with an electrically conducting material; and depositing an anode current collector metal layer on a bottom surface of the anode layer.Type: ApplicationFiled: April 8, 2022Publication date: July 21, 2022Inventor: Martin Andreas Olsson
-
Patent number: 11316165Abstract: There is provided a solid-state battery layer structure which may include an anode current collector metal layer, an anode layer arranged on the anode current collector metal layer, a solid electrolyte layer arranged on the anode layer laterally, a cathode layer arranged on the solid electrolyte layer, and a cathode current collector metal layer, and a plurality of nanowire structures comprising silicon and/or gallium nitride, wherein said nanowire structures are arranged on the anode layer and, wherein said nanowire structures are laterally and vertically enclosed by the solid electrolyte layer, wherein the anode layer comprises silicon and a plurality of metal vias connecting the plurality of nanowire structures with the anode current collector metal layer. Methods for producing solid-state battery layer structures are also provided.Type: GrantFiled: May 14, 2021Date of Patent: April 26, 2022Assignee: Epinovatech ABInventor: Martin Andreas Olsson
-
Publication number: 20210327712Abstract: A reinforced thin-film device (100, 200, 500) including a substrate (101) having a top surface for supporting an epilayer; a mask layer (103) patterned with a plurality of nanosize cavities (102, 102?) disposed on said substrate (101) to form a needle pad; a thin-film (105) of lattice-mismatched semiconductor disposed on said mask layer (103), wherein said thin-film (105) comprises a plurality of in parallel spaced semiconductor needles (104, 204) of said lattice-mismatched semiconductor embedded in said thin-film (105), wherein said plurality of semiconductor needles (104, 204) are substantially vertically disposed in the axial direction toward said substrate (101) in said plurality of nanosize cavities (102, 102?) of said mask layer (103), and where a lattice-mismatched semiconductor epilayer (106) is provided on said thin-film supported thereby.Type: ApplicationFiled: April 23, 2019Publication date: October 21, 2021Inventor: Martin Andreas Olsson
-
Publication number: 20210265632Abstract: There is provided a solid-state battery layer structure which may include an anode current collector metal layer, an anode layer arranged on the anode current collector metal layer, a solid electrolyte layer arranged on the anode layer laterally, a cathode layer arranged on the solid electrolyte layer, and a cathode current collector metal layer, and a plurality of nanowire structures comprising silicon and/or gallium nitride, wherein said nanowire structures are arranged on the anode layer and, wherein said nanowire structures are laterally and vertically enclosed by the solid electrolyte layer, wherein the anode layer comprises silicon and a plurality of metal vias connecting the plurality of nanowire structures with the anode current collector metal layer. Methods for producing solid-state battery layer structures are also provided.Type: ApplicationFiled: May 14, 2021Publication date: August 26, 2021Inventor: Martin Andreas Olsson