Patents by Inventor Andreas Spitzer
Andreas Spitzer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20130264654Abstract: An integrated circuit includes a semiconductor body with a first semiconductor layer and a second semiconductor layer arranged adjacent the first semiconductor layer in a vertical direction of the semiconductor body. The integrated circuit further includes a switching device with a control terminal and a load path between a first load terminal and a second load terminal, and a rectifier element connected in parallel with at least one section of the load path. The switching device is integrated in the first semiconductor layer and the rectifier element is integrated in the second semiconductor layer.Type: ApplicationFiled: April 6, 2012Publication date: October 10, 2013Applicant: INFINEON TECHNOLOGIES DRESDEN GMBHInventors: Rolf Weis, Andreas Spitzer
-
Patent number: 7531405Abstract: A polycrystalline dielectric layer is formed wherein the dielectric layer comprises a first dielectric material containing an oxide or nitride and a second material contributing to less than 1% in weight to the dielectric layer, forming a non-conductive oxide or nitride having an enthalpy lower than the enthalpy of the first dielectric material such that a leakage current along grain boundaries of the first dielectric material is reduced.Type: GrantFiled: February 28, 2005Date of Patent: May 12, 2009Assignee: Qimonds AGInventors: Andreas Spitzer, Elke Erben
-
Publication number: 20070278549Abstract: An integrated semiconductor memory includes at least one memory cell having at least one transistor which forms an inversion channel in the switched-on state. The transistor comprises a structure element having a first source/drain region, a second source/drain region, and a region arranged between the first and the second source/drain region. The structure element is insulated from a semiconductor substrate by an insulation layer, a gate dielectric is arranged on the structure element, and a word line is arranged on the gate dielectric.Type: ApplicationFiled: July 10, 2007Publication date: December 6, 2007Applicant: QIMONDA AGInventor: Andreas Spitzer
-
Publication number: 20070210367Abstract: A storage capacitor includes a first electrode layer, second electrode layer and a dielectric interlayer arranged between the first electrode layer and the second electrode layer. The dielectric interlayer contains a high-k dielectric and at least one silicon-containing component.Type: ApplicationFiled: November 30, 2006Publication date: September 13, 2007Applicant: QIMONDA AGInventors: Henry Bernhardt, Thomas Hecht, Michael Stadtmueller, Christian Kapteyn, Uwe Schroder, Yeong-Kwan Kim, Andreas Spitzer
-
Patent number: 7241657Abstract: The invention relates to an integrated semiconductor memory with at least one memory cell having at least one transistor which forms an inversion channel in the switched-on state. The transistor comprises a structure element having a first source/drain region, a second source/drain region and a region arranged between the first and the second source/drain region, the structure element is insulated from a semiconductor substrate by an insulation layer, a gate dielectric being arranged on the structure element and a word line being arranged on the gate dielectric.Type: GrantFiled: November 22, 2005Date of Patent: July 10, 2007Assignee: Infineon Technologies AGInventor: Andreas Spitzer
-
Publication number: 20060192271Abstract: A polycrystalline dielectric layer is formed wherein the dielectric layer comprises a first dielectric material containing an oxide or nitride and a second material contributing to less than 1% in weight to the dielectric layer, forming a non-conductive oxide or nitride having an enthalpy lower than the enthalpy of the first dielectric material such that a leakage current along grain boundaries of the first dielectric material is reduced.Type: ApplicationFiled: February 28, 2005Publication date: August 31, 2006Applicant: Infineon Technologies AGInventors: Andreas Spitzer, Elke Erben
-
Publication number: 20060071261Abstract: The invention relates to an integrated semiconductor memory with at least one memory cell having at least one transistor which forms an inversion channel in the switched-on state. The transistor comprises a structure element having a first source/drain region, a second source/drain region and a region arranged between the first and the second source/drain region, the structure element is insulated from a semiconductor substrate by an insulation layer, a gate dielectric being arranged on the structure element and a word line being arranged on the gate dielectric.Type: ApplicationFiled: November 22, 2005Publication date: April 6, 2006Inventor: Andreas Spitzer
-
Patent number: 6995418Abstract: The invention relates to an integrated semiconductor memory with at least one memory cell having at least one transistor which forms an inversion channel in the switched-on state. The transistor comprises a structure element having a first source/drain region, a second source/drain region and a region arranged between the first and the second source/drain region, the structure element is insulated from a semiconductor substrate by an insulation layer, a gate dielectric being arranged on the structure element and a word line being arranged on the gate dielectric.Type: GrantFiled: May 7, 2004Date of Patent: February 7, 2006Assignee: Infineon Technologies, AGInventor: Andreas Spitzer
-
Publication number: 20060022248Abstract: Electronic data memory device for a high read current The invention provides a memory device arranged on a substrate (401) and having at least one memory cell (100) The memory cell comprises a storage capacitor (200) for storing an electrical charge and a selection transistor (300) for selecting the memory cell (100). The selection transistor comprises a first conduction electrode (301), a second conduction electrode (302) and a control electrode (303) , the control electrode (303) being provided by a gate unit (400) having a fin (405) projecting from the substrate (401), which fin is surrounded by a gate oxide layer (406) and a gate electrode layer (403) in such a way that first and second gate elements (408a, 408b) are provided at opposite lateral areas of the fin (405), a third gate element (408c) being provided at an area of the fin (405) that is parallel to the surface of the substrate (401).Type: ApplicationFiled: June 27, 2005Publication date: February 2, 2006Inventors: Bjorn Fischer, Franz Hofmann, Richard Luyken, Andreas Spitzer
-
Patent number: 6992345Abstract: An integrated semiconductor memory is disclosed having selection transistors which can be formed at a respective ridge. The ridge can be arranged on an insulation layer. In the ridge the first source/drain region can be formed at one lateral end of the ridge and the second source/drain region can be formed at another lateral end of the ridge. The longitudinal sides of the ridge and a top side of the ridge can be covered with a layer stack including a gate dielectric and a gate electrode. High write-read currents can be achieved in the on state of the selection transistors and leakage currents occurring in the off state can be reduced.Type: GrantFiled: December 5, 2003Date of Patent: January 31, 2006Assignee: Infineon Technologies, AGInventors: Gerhard Enders, Andreas Spitzer
-
Publication number: 20050041495Abstract: The invention relates to an integrated semiconductor memory (10) with at least one memory cell (1) having at least one transistor (3) which forms an inversion channel (34) in the switched-on state, the transistor (3) having a structure element (4) having a first source/drain region (5), a second source/drain region (6) and a region (4b) arranged between the first (5) and the second source/drain region (6), the structure element (4) being insulated from a semiconductor substrate (20) by an insulation layer (11), a gate dielectric (9) being arranged on the structure element (4) and a word line (16) being arranged on the gate dielectric (9), the gate dielelctric (9) being a high-resistance tunnel contact having a first region (31), the layer thickness (d) of which is so small that, in the switched-off state of the transistor (3), majority charge carriers generated thermally in the structure element (4) pass into the word line (16) by direct tunneling through the gate dielectric (9), and the entire region (4b) ofType: ApplicationFiled: May 7, 2004Publication date: February 24, 2005Inventor: Andreas Spitzer
-
Publication number: 20040136227Abstract: An integrated semiconductor memory having selection transistors can be formed at a web. The web can be arranged on an insulation layer. The first source/drain region can be arranged on the insulation layer at one lateral end of the web and the second source/drain region can be arranged on the insulation layer at another lateral end of the web. The longitudinal sides of the web and a top side of the web can be covered with a layer sequence including a gate dielectric and a gate electrode. High write-read currents can be achieved in the on state of the selection transistors and leakage currents occurring in the off state can be reduced.Type: ApplicationFiled: December 5, 2003Publication date: July 15, 2004Inventors: Gerhard Enders, Andreas Spitzer
-
Publication number: 20020025377Abstract: In addition to the starting gases containing the elements of the solid-state layer to be deposited, at least one auxiliary substance is introduced into the reaction space of a reactor chamber. This auxiliary substance contains molecules which have a dipole moment and which have the property of briefly attaching themselves during the deposition process to the substrate surface with a dipole moment perpendicular to the substrate surface. In this way, the crystal structure of the solid-state layer to be grown on is dictated.Type: ApplicationFiled: August 24, 2001Publication date: February 28, 2002Inventors: Alfred Kersch, Andreas Spitzer
-
Patent number: 6165835Abstract: In producing a silicon capacitor, hole structures (2) are created in a silicon substrate (1), at the surface of which structures a conductive zone (3) is created by doping and whose surface is provided with a dielectric layer (4) and a conductive layer (5), without filling the hole structures (2). To compensate mechanical strains upon the silicon substrate (1) which are effected by the doping of the conductive zone (3), a conformal auxiliary layer (6) is formed on the surface of the conductive layer (5), which auxiliary layer is under a compressive mechanical stress.Type: GrantFiled: July 20, 1999Date of Patent: December 26, 2000Assignee: Siemens AktiengesellschaftInventors: Hermann Wendt, Hans Reisinger, Andreas Spitzer, Reinhard Stengl, Ulrike Gruning, Josef Willer, Wolfgang Honlein, Volker Lehmann
-
Patent number: 5360759Abstract: For manufacturing a component with porous silicon, two highly doped regions with a lightly doped region arranged between them are formed in a silicon wafer. The dopant concentrations are thereby set such that porous silicon arises in the lightly doped region in a subsequent anodic etching. Light-emitting diodes or light-controlled bipolar transistors can be manufactured in this way.Type: GrantFiled: September 17, 1993Date of Patent: November 1, 1994Assignee: Siemens AktiengesellschaftInventors: Reinhard Stengl, Wolfgang Hoenlein, Volker Lehmann, Andreas Spitzer