Abstract: Hybrid image sensors with on-chip image deblur (and associated systems, devices, and methods) are disclosed herein. In one embodiment, an image sensor includes (a) a plurality of CMOS image sensor (CIS) pixels configured to capture CIS data corresponding intensity of light incident on CIS pixels of the plurality of CIS pixels, (b) an event vision sensor (EVS) pixel configured to capture EVS data corresponding to events detected in light incident on the EVS pixel, and (c) a deblur circuit configured to generate deblurred image data based on the CIS data and an accumulation of events in the EVS data. The deblur circuit can be configured to compute the accumulation of events, such as using an event-based double integral model.

Abstract: A pixel circuit includes a pixel array and a color filter. The pixel array includes pixels arranged in rows and columns, and each pixel includes a photodiode configured to photogenerate image charge in response to incident light, and a transfer transistor coupled to the photodiode to transfer the image charge out from the photodiode. The color filter array includes color filters each having one of a plurality of colors and disposed over at least one of the pixels. Each of the pixels is coupled to a first readout circuit, and the plurality of pixels includes a first subset of the pixels not coupled to a second readout circuit and a second subset of the pixels coupled to the second readout circuit. Two diagonally arranged pixels are coupled together to share a floating diffusion, and the two diagonally arranged pixels coupled together are disposed underneath color filters of a same color.

Abstract: A pixel circuit includes a pixel array and a color filter. The pixel array includes a plurality of pixels arranged in rows and columns, each pixel including four photodiodes, a floating diffusion, and four transfer transistors. The color filter array includes a plurality of color filters each having one of a plurality of colors and disposed over at least one of the pixels. Each of the plurality of pixels is coupled to a first readout circuit, and the plurality of pixels includes (i) a first subset of the pixels not coupled to a second readout circuit and (ii) a second subset of the pixels coupled to the second readout circuit. Floating diffusions of two diagonally arranged pixels are coupled together, and the two diagonally arranged pixels coupled together are disposed underneath color filters of a same color.

Abstract: Hybrid image sensors with on-chip image deblur and rolling shutter distortion correction (and associated systems, devices, and methods) are disclosed herein. In one embodiment, an image sensor includes (a) an event driven sensing array including one or more event vision sensor (EVS) pixels, each configured to capture event data corresponding to contrast information of light incident on the EVS pixel; (b) a pixel array including a plurality of CMOS image sensor (CIS) pixels arranged in one or more CIS pixel rows, each CIS pixel configured to capture CIS data corresponding to intensity of light incident on the CIS pixel, and (c) a rolling shutter distortion correction circuit configured to correct the CIS data for rolling shutter distortion using the event data.

Abstract: Reconfigurable single-photon avalanche diode (SPAD) sensors with column-level timecode distribution (and associated systems, devices, and methods) are disclosed herein. In one embodiment, an imaging system includes a pixel array including a plurality of SPAD sensors arranged in a plurality of rows and columns, and a plurality of timers. Each timer corresponds to a respective column and can generate timecodes based on a clock signal. Each SPAD sensor of a given column can receive the timecodes generated by the timer corresponding to the given column. The system can include calibration circuitry configured to sample skew along one or more columns of the pixel array, and a clock distribution network to distribute the clock signal to the timers and the calibration circuitry.

Abstract: Reconfigurable single-photon avalanche diode (SPAD) sensors (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a reconfigurable SPAD sensor includes a plurality of SPADs configured to detect photon events corresponding to incident light from an external scene. A summation circuit is coupled to the SPADs and configured to generate sums of photon events detected by the SPADs using a synchronous summation technique (SST). An in-pixel static random-access memory (SRAM) is coupled to the summation circuit and configured to store photon event counts corresponding to at least one SPAD of the plurality. In some embodiments, the reconfigurable SPAD sensor further comprises a ripple counter circuit coupled to the SPADs. The SPAD sensor is reconfigurable to transition between operating in a depth mode to obtain distance information related to objects within the external scene and operating in an intensity mode to obtain intensity information corresponding to the incident light.

Abstract: Hybrid image sensors with multiple operating modes are disclosed herein. In one embodiment, a pixel arrangement includes a first photosensor, a first floating diffusion, a second photosensor, a second floating diffusion, and a mode switch. The mode switch can include (a) a first switch selectively coupling the second floating diffusion to the first floating diffusion, and (b) a second switch configured to selectively couple the second floating diffusion to event vision sensor (EVS) readout circuitry. The mode switch can be used to transition the pixel arrangement between (i) a first mode in which the pixel arrangement is controllable to output intensity information corresponding to first light incident on the first photosensor and/or second light incident on the second photosensor, and (ii) a second mode in which the pixel arrangement is controllable to output contrast information corresponding to the first light and/or the second light.

Abstract: Pixels with multiple operating modes (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a pixel arrangement includes a pixel including a first photosensor, a second photosensor, a floating diffusion, a first event vision sensor (EVS) connection coupling the pixel to first EVS readout circuitry and configured to receive first charge from the first photosensor, and a second EVS connection coupling the pixel to second EVS readout circuitry and configured to receive second charge from the second photosensor. The pixel further includes a first transfer transistor selectively coupling the first photosensor to the floating diffusion, a second transfer transistor selectively coupling the first photosensor to the first EVS connection, and a third transfer transistor selectively coupling the second photosensor to the floating diffusion.

Abstract: Event vision sensors with digital event detection are disclosed herein. In one embodiment, an image sensor includes an EVS pixel with a photosensor, an integrating-type photo-detecting stage, and in-pixel sampling circuitry including multiple sampling nodes. An analog-to-digital converter (ADC) is coupled to the in-pixel sampling circuitry and converts analog irradiance levels into digital signals. Event detection circuitry coupled to the ADC computes event signals based on temporal contrast differences between corresponding digital signals output by the ADC and a contrast threshold. The in-pixel sampling circuitry samples integrated reference and momentary integrated signal irradiance levels during different operational phases. The event detection circuitry performs correlated double sampling operations to compute digital difference signals and asserts an event signal when the temporal contrast difference exceeds the contrast threshold.

Abstract: Event vision sensors with digital event detection are disclosed herein. In one embodiment, an image sensor includes an EVS pixel with a photosensor, an integrating-type photo-detecting stage, and in-pixel sampling circuitry including multiple circuit branches. An analog-to-digital converter (ADC) is coupled to the in-pixel sampling circuitry and converts analog irradiance levels into digital signals. Event detection circuitry coupled to the ADC computes event signals based on (i) temporal contrast differences between corresponding digital signals output by the ADC and (ii) a contrast threshold. The in-pixel sampling circuitry can include branches for sampling momentary integrated signal irradiance levels and integrated reference irradiance levels. The event detection circuitry can assert event signals when temporal contrast differences exceed the threshold, indicating event detection during an exposure period.

Abstract: Event vision sensors with digital event detection (and associated systems, devices, and methods) are disclosed herein. In one embodiment, an image sensor includes an EVS pixel, an analog-to-digital converter (ADC), and event detection circuitry. The EVS pixel can include a photosensor, an integrating-type photo-detecting stage, and in-pixel sampling circuitry comprising a plurality of circuit branches that are each configured to perform correlated double sampling (CDS) operations to sample integrated irradiance levels. The ADC can be coupled to the in-pixel sampling circuitry and configured to convert the integrated irradiance levels into corresponding digital signals. The event detection circuitry can be coupled to the ADC and configured to generate event signals based at least in part on temporal contrast differences between the corresponding digital signals output by the ADC and a contrast threshold.

Abstract: Hybrid image sensors with multiple operating modes are disclosed herein. In one embodiment, a pixel arrangement includes a first photosensor, a first floating diffusion, a second photosensor, a second floating diffusion, and a mode switch. The mode switch can include (a) a first switch selectively coupling the second floating diffusion to the first floating diffusion, and (b) a second switch configured to selectively couple the second floating diffusion to event vision sensor (EVS) readout circuitry. The mode switch can be used to transition the pixel arrangement between (i) a first mode in which the pixel arrangement is controllable to output intensity information corresponding to first light incident on the first photosensor and/or second light incident on the second photosensor, and (ii) a second mode in which the pixel arrangement is controllable to output contrast information corresponding to the first light and/or the second light.

Abstract: Hybrid CIS/EVS image sensors are disclosed herein. In one embodiment, a pixel arrangement includes a plurality of pixels and a color filter array. Each of the plurality of pixels can include a photosensor, a floating diffusion, a transfer transistor, and an EVS transistor configured to selectively couple the photosensor to an event driven circuit corresponding to the pixel. The color filter array can include a plurality of color filters arranged in a mosaic pattern over photosensors of the plurality of pixels such that the photosensor of a first pixel of the plurality of pixels corresponds to a first color and the photosensor of a second pixel of the plurality of pixels corresponds to a second color different from the first color. The event driven circuits corresponding to the plurality of pixels can be (a) different from one another and (b) selectively coupled to one another via a common node.

Abstract: A method for wafer testing an event-based vision sensor (EVS), the EVS sensor comprising a photodiode, a logarithmic amplifier configured to generate an amplified signal in response to voltage received by the photodiode, a first buffer, and a bitline (BL), the method including determining a performance of the logarithmic amplifier, where determining the performance includes irradiating a pixel array by sweeping irradiance, feeding an output of the pixel array into the BL, probing one or more output of the BL with an analog-to-digital converter (ADC), and monitoring the one or more outputs of the BL, wherein the performance is determined based upon the one or more outputs of the BL.

Abstract: Reconfigurable hybrid event-based vision sensor and CMOS image sensor systems (an associated systems, devices, and methods) are disclosed. In one embodiment, a hybrid image sensor includes a pixel circuit array with pixel circuits reconfigurable between (i) a CMOS image sensor (CIS) configuration for obtaining intensity information and (ii) an event vision sensor (EVS) configuration for obtaining contrast information. Control circuitry can reconfigure a first subset of pixel circuits into the EVS configuration based on detected motion in an external scene, switching the hybrid image sensor between (a) a CIS-only mode in which all pixel circuits operate in the CIS configuration and (b) a hybrid mode in which the first subset operates in the EVS configuration and a second subset operates in the CIS configuration. The control circuitry can control the number of pixel circuits included in the first subset based on luminance conditions in the external scene.

Abstract: A pixel circuit includes a photodiode configured to photogenerate charge in response to reflected modulated light incident upon the photodiode. A first floating diffusion is configured to store a first portion of charge photogenerated in the photodiode. A first transfer transistor is configured to transfer the first portion of charge from the photodiode to the first floating diffusion in response to a first phase signal. A first storage node is configured to store the first portion of charge from the first floating diffusion. A first decoupling circuit has a first output responsive to a first input. The first input is coupled to the first floating diffusion and the first output is coupled to first storage node. A voltage swing at the first output is greater than a voltage swing at the first input.

Abstract: A device has a first and second PPD sensor configured for placement over an artery; a camera between the first and second PPD sensors; and a processor having memory with firmware for determining pulse transit time (PTT) between the PPD sensors, and determines blood pressure (BP) therefrom using a calibrated conversion from PTT to BP. The firmware also obtains initial and subsequent images of the artery, extracts features, and adjusts calibrated conversion from PTT to BP based upon features extracted from the initial and subsequent images of the artery. In embodiments the processor enhances the initial and subsequent images of the artery using a structured light tomographic enhancement process. A method uses first and second PPD sensors placed over an artery to determine pulse transit time; obtains initial and subsequent images of the artery with a camera; and uses features extracted from the initial and subsequent images of the artery to adjust a calibrated conversion from PTT to BP.

Abstract: Event vision sensors with defect pixel suppression (and associated methods) are disclosed herein. In one embodiment, an event vision sensor includes an array of event vision pixels and an event signal processor. The event signal processor is configured to identify event vision pixels of the array that are defective based on noise event occurrence firing rates corresponding to the event vision pixels. The noise event occurrence firing rate for each event vision pixel can be based on inter-arrival times or a noise event rate corresponding to that event vision pixel. Each event vision pixel can include internal circuitry (e.g., a memory component, such as a latch) that can, when the event vision pixel is identified as defective, be used to disable the event vision pixel from detecting events or to mask an output of the event vision pixel such that events are not read out of the event vision pixel.

Abstract: A time-of-flight sensor includes an integrated circuit chip in which a voltage regulator and a load are disposed. The load includes a grouping of pixel circuits and modulation driver that is supplied power from the voltage regulator. The grouping of pixel circuits included in a pixel array disposed in the integrated circuit trip. Each one of the pixel circuits includes a photodiode configured to photogenerate charge in response to reflected modulated light, a floating diffusion configured to store a portion of charge photogenerated in the photodiode, and transfer transistor to transfer the portion of charge from the photodiode to the floating diffusion in response to a phase modulation signal generated by the modulation driver. A feedback circuit is coupled between the load and the voltage regulator and is coupled to receive a feedback signal from the feedback circuit in response to the load.

Abstract: A mixed analog/digital in-memory computing device implements matrix vector multiplication with reduced noise for use by a deep neural network (DNN). For each row of a cross-bar array a digital multiplier is split into a least significant (LS) portion and a most significant (MS) portion of different sizes that are preloaded into two cells on one row and two different columns of the cross-bar array. An input activation (IA) value is driven onto input conductors of each row and an analog-to-digital converter (ADC) converts output signals from the two columns as a MS partial sum and a LS partial sum. A gain is applied to the MS partial sum and added to the LS partial sum to form a resulting value for one node of the DNN.