Abstract: The integrated memory chip has an external control terminal, a dynamic memory, and a control circuit for controlling a memory access to the dynamic memory. The control circuit is connected to the external control terminal, for receiving an access command indicating the beginning of a memory access. The control circuit further has an output, which is connected to the dynamic memory, for outputting at least one activation signal, read command or write command and precharge command generated from the access command. This makes it possible, in the case of use in a data processing system, to dispense with a DRAM controller provided outside the memory chip.

Abstract: A data output interface, in particular for semiconductor memories, provides a plurality of output drivers for providing data output signals in a manner dependent on a read command and a clock signal. In order to signal to a microprocessor that can be connected to the data output that data are provided, a data provision signal is additionally provided by a further output driver. The arrangement described can preferably be used for DDR-SDRAMs and enables particularly high clock frequencies.

Abstract: The invention provides a circuit arrangement for scalable output drivers, symmetrically arranged driver transistor groups being provided which each have transistor pairs having the same transistor line width. If there are m different driver transistor groups present, 2(n−1) different gradations result, thereby achieving good scalability. Furthermore, a transistor line width that is simple to design is provided for all transistors of all driver transistor groups, thereby providing identical electrical properties with respect to an output terminal unit.

Abstract: A device for generating memory-internal command signals from a memory operation command is provided comprising a command input for receiving a memory operation command for performing a memory operation in a memory system, a clock signal input for receiving an external clock signal and an output for applying the memory-internal command signal to a command signal line of the memory system. The device further includes a command signal generating means which is implemented in order to generate the memory-internal command signal using the memory operation command at a time which depends on the memory-internal command signal and which is selectively settable synchronous with a rising or synchronous with a falling edge of the external clock signal.

Abstract: The voltage supply provides voltages to an electronic circuit requiring at least two different supply voltages. A plurality of standby supply voltages with different levels are obtained from the highest supply voltage with the aid of a voltage divider.

Abstract: An integrated circuit containing a number of subcircuits is described. Each of the subcircuits contains a driver circuit for driving in each case one controllable voltage source on the basis of a reference value. The driver circuit has a memory unit for storing a reference value and a terminal for outputting a first reference value or for inputting a second reference value. A signal line, which is used for transmitting a signal, is connected to the terminal of the driver circuit of each of the subcircuits. The driving by the driver circuit is effected in each subcircuit on the basis of a common reference value that is transmitted via the signal line. Thus, the time needed for setting the reference values for all subcircuits is relatively short.

Abstract: An integrated memory is described that has memory blocks with column lines and row lines as well as at least one redundancy row line for replacing in each case one of the row lines in any of the memory blocks. In addition, each memory and memory block has a deactivation unit for deactivating the memory block. The integrated memory has deactivation lines, each of which is connected to an input of the deactivation unit of one of the memory blocks. Each memory block has a deactivation decoder that is connected at the output end to all the deactivation lines. If one of the row lines of a first memory block of the memory blocks is replaced by a redundancy row line of a second memory block of the memory blocks, the deactivation decoder of the second memory block deactivates the first memory block via the corresponding deactivation line.