Abstract: An integrated circuit comprises a first conductive lines and second lines as well as contact structures being in contact with the first and second conductive lines. The first conductive lines are arranged in a first metallization level, and second conductive lines are arranged in a second metallization level arranged above the first metallization level. The second conductive lines are arranged above the contact structures, and a pitch of neighboring contact structures is equal to a pitch of neighboring second conductive lines. The distance between neighboring contact structures is smaller than 100 nm.

Abstract: The invention relates to a wood substitute material for wood-encased pencils, comprising the following ingredients: 15-3.0% by weight of at least one polymeric binder, 50-80% by weight of at least one organic filler, 0-20% by weight of at least one inorganic filler, 0.5-5% by weight of at least one adhesion promoter, 1-30% by weight of at least one wax, 0-10% by weight of at least one colour pigment, and 0-10% by weight of at least one additive, the at least one adhesion promoter forming a chemical bond between the at least one polymeric binder and the at least one organic filler, a ratio of the at least one adhesion promoter and the at least one wax in the range from 1:2 to 1:6 being formed, and the sum of organic and inorganic filler being not more than 80% by weight.

Abstract: The invention relates to a writing, drawing, decorating or cosmetic pencil comprising a colour-delivering, polymer-bonded lead and a polymer-bonded wood substitute material, the wood substitute material at least partly covering or surrounding the lead along its length, there being disposed, between the lead and the wood substitute material, at least one adhesion promoter layer, the lead and the wood substitute material each comprising at least one polymer, the at least one polymer in the lead being incompatible with the at least one further polymer in the wood substitute material, and the at least one adhesion promoter layer coupling on the one hand to the at least one polymer in the lead and on the other hand to the at least one further polymer in the wood substitute material.

Abstract: The invention relates to a polymer-bonded pencil lead for writing, drawing or painting devices, in particular for lead pencils or colored pencils, comprising a polymer binder, at least one wax and at least one filler, wherein the pencil lead further comprises 0.1 to 5 wt.-% palm oil.

Abstract: An integrated circuit includes a memory array portion and a support circuitry portion arranged on a semiconductor substrate. An insulative layer is formed on the semiconductor substrate. Data storage capacitors are located in the memory array portion and extending through the insulative layer. Non-data storage capacitors are located in the support circuitry portion and terminating above the insulative layer.

Abstract: An unburnt color lead for writing devices, drawing devices and painting devices, includes at least one coloring material, at least one binder, at least one organic lubricant which is solid at room temperature, and at least one filler material whose particles essentially have a disk-shaped configuration. The color lead contains 20 to 80 weight % of the at least one filler material, and the color lead contains at least 20 weight % hexagonal bornitride as a first filler material.

Abstract: A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of pillars. Buried word lines extend within the insulating trenches along the rows of pillars. Bit line trenches are formed between columns of pillars. Bit lines extend perpendicular to the word lines in lower portions of the bit line trenches. A first and a second column of pillars face adjacent each bit line. Each bit line is coupled to the active areas in the pillars of the first column of pillars via a single sided bit line contact formed from polycrystalline silicon and is insulated from the active areas of the pillars of the second column of pillars.

Abstract: Structures and methods of forming through substrate vias are disclosed. In one embodiment, the method includes forming a through substrate opening from a top surface of a substrate, the top surface including active devices, and filling the first through substrate opening with an ancillary material. A conductive capping layer is formed over the ancillary material to cap the first through substrate opening. The substrate is thinned from a back surface to expose a portion of the ancillary material, the back surface being opposite to the top surface. The ancillary material is removed from the first through substrate opening, and a conductor is formed by filling a conductive material into the through substrate opening.

Abstract: Structures and methods of forming stacked chips are disclosed. In one embodiment, a first chip is disposed over a second chip, a top surface of the first and the second chip includes active circuitry. A first through substrate via is disposed within the first chip, the first through substrate via includes a protruding tip projecting below a bottom surface of the first chip, the bottom surface being opposite the top surface. A second through substrate via is disposed on the second chip, the second through substrate via including an opening, wherein the first protruding tip of the first chip is disposed within the opening of the second chip.

Abstract: An integrated circuit includes a memory array portion and a support circuitry portion arranged on a semiconductor substrate. An insulative layer is formed on the semiconductor substrate. Data storage capacitors are located in the memory array portion and extending through the insulative layer. Non-data storage capacitors are located in the support circuitry portion and terminating above the insulative layer.

Abstract: An integrated circuit on a substrate comprises a buffer capacitor in a buffer region. The buffer capacitor comprises a buffer electrode arranged at least partially in a recess, and a dielectric layer disposed between the buffer electrode and the substrate.

Abstract: An actuator for an active chassis of a motor vehicle is proposed which includes a body spring and a vibration damper, and which incorporates a hydraulic or pneumatic positioning cylinder (3) and a compensation spring (2). The actuator (1) is so designed and positioned that the static body mass (13) is borne by the compensation spring (2).

Abstract: An integrated circuit comprises a first conductive lines and second lines as well as contact structures being in contact with the first and second conductive lines. The first conductive lines are arranged in a first metallization level, and second conductive lines are arranged in a second metallization level arranged above the first metallization level. The second conductive lines are arranged above the contact structures, and a pitch of neighboring contact structures is equal to a pitch of neighboring second conductive lines. The distance between neighboring contact structures is smaller than 100 nm.

Abstract: A semiconductor substrate is provided comprising a plurality of contact pads arranged on a horizontal surface of the semiconductor substrate. Pillars of a first sacrificial material are formed on the contact pads. A first dielectric layer is deposited thus covering at least said pillars. A first conductive layer is deposited between said pillars covered with the first dielectric layer. The pillars are removed thus providing trenches in the first conductive layer having walls covered with the dielectric layer. A second conductive layer is deposited on the first dielectric layer in the trench. A second dielectric layer is deposited such that at least the second conductive layer in the trench is covered by the second dielectric layer. A third conductive layer is deposited on the second dielectric layer.

Abstract: A method for determining a control standard of an active steering device (10) of a vehicle (1) controllable by a control device (11). A driving dynamic of the vehicle (1) is influenced according to the control standard. The control standard is determined according to a nominal yawing rate calculated at least with reference to different actual operating parameters of the vehicle and one dynamic vehicle state determined according to the nominal yawing rate and actual operating state parameters. The control standard is superimposed on a steering transit angle preset by a driver so that an existing actual yawing rate is changed in direction of the nominal yawing rate.

Abstract: A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of pillars. Buried word lines extend within the insulating trenches along the rows of pillars. Bit line trenches are formed between columns of pillars. Bit lines extend perpendicular to the word lines in lower portions of the bit line trenches. A first and a second column of pillars face adjacent each bit line. Each bit line is coupled to the active areas in the pillars of the first column of pillars via a single sided bit line contact formed from polycrystalline silicon and is insulated from the active areas of the pillars of the second column of pillars.

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate with a main surface; forming a wiring metal layer above said main surface; forming a doped getter layer on said wiring metal layer; and forming at least one additional wiring metal layer on said doped getter layer. The present invention also provides a corresponding integrated semiconductor structure and a semiconductor memory device.

Abstract: A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of pillars. Buried word lines extend within the insulating trenches along the rows of pillars. Bit line trenches are formed between columns of pillars. Bit lines extend perpendicular to the word lines in lower portions of the bit line trenches. A first and a second column of pillars face adjacent each bit line. Each bit line is coupled to the active areas in the pillars of the first column of pillars via a single sided bit line contact formed from polycrystalline silicon and is insulated from the active areas of the pillars of the second column of pillars.

Abstract: An unburnt color lead for writing devices, drawing devices and painting devices, includes at least one coloring material, at least one binder, at least one organic lubricant which is solid at room temperature, and at least one filler material whose particles essentially have a disk-shaped configuration. The color lead contains 20 to 80 weight % of the at least one filler material, and the color lead contains at least 20 weight % hexagonal bornitride as a first filler material.

Abstract: An active chassis for a motor vehicle is proposed that comprises an actuator (2) with a hydraulic or pneumatic positioning cylinder (3) and a vibration absorber (4), wherein the actuator (2) features a partial load-bearing mounting spring (5), where a partial load-bearing second mounting spring (1) is connected in parallel to the actuator (2), the vibration absorber (4) is connected in parallel to the mounting spring (5) of the actuator (2) and the adjusting cylinder (3) is connected in series to the mounting spring (5) and to the vibration absorber (4).