Patents by Inventor Andreas Voerckel
Andreas Voerckel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047207Abstract: A method of forming a semiconductor device includes providing a base substrate comprising SiC and a growth surface extending along a plane that is angled relative to a first crystallographic plane of the SiC from the base substrate, forming first and second trenches in the base substrate that extend from the growth surface into the base substrate, epitaxially forming a first SiC layer on the growth surface of the base substrate by a step-controlled epitaxy technique, and epitaxially forming a second SiC layer on the first SiC layer, wherein the first SiC layer is a layer of ?-SiC, and wherein the second SiC layer is a layer of ?-SiC.Type: ApplicationFiled: August 2, 2022Publication date: February 8, 2024Inventors: Christian Zmoelnig, Tobias Franz Wolfgang Hoechbauer, Andreas Voerckel, Hans Weber
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Patent number: 11842938Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.Type: GrantFiled: November 30, 2021Date of Patent: December 12, 2023Assignee: Infineon Technologies AGInventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
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Publication number: 20230051830Abstract: A transistor device and a method for forming a transistor device are disclosed. The transistor device includes: a SiC semiconductor body that includes a first semiconductor layer and a second semiconductor layer formed on top of the first semiconductor; a trench structure extending from a first surface of the semiconductor body through the second semiconductor layer into the first semiconductor layer; a drain region arranged in the first semiconductor layer; and a plurality of transistor cells each coupled between the drain region and a source node. The trench structure subdivides the second semiconductor layer into a plurality of mesa regions and includes at least one cavity. At least one of the plurality of transistor cells is at least partially integrated in each of the mesa regions.Type: ApplicationFiled: August 12, 2022Publication date: February 16, 2023Inventors: Andreas Voerckel, Hans Weber, Tobias Franz Wolfgang Hoechbauer
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Publication number: 20230045841Abstract: A semiconductor device includes a transistor. The transistor may include a gate electrode in gate trenches formed in a first portion of a silicon carbide substrate and extending in a first horizontal direction. The gate trenches pattern the first portion into ridges. The transistor may further include a source region, a channel region, and a drift region. The source region, channel region and part of the drift region may be arranged in the ridges. A current path from the source region to the drift region may extend in a depth direction of the silicon carbide substrate. The transistor may further include a body contact portion arranged in a second portion of the silicon carbide substrate. The second portion is adjacent to the first portion and extends in a second horizontal direction intersecting the first horizontal direction.Type: ApplicationFiled: August 9, 2022Publication date: February 16, 2023Inventor: Andreas Voerckel
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Patent number: 11342187Abstract: Forming a semiconductor arrangement includes providing a first semiconductor layer having a first surface, forming a first plurality of trenches in the first surface of the first semiconductor layer, each of the trenches in the first plurality having first and second sidewalls that extend from the first surface to a bottom of the respective trench, implanting first type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, implanting second type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, and annealing the semiconductor arrangement to simultaneously activate the first type dopant atoms and the second type dopant atoms.Type: GrantFiled: April 16, 2020Date of Patent: May 24, 2022Assignee: Infineon Technologies Austria AGInventors: Anton Mauder, Hans Weber, Franz Hirler, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
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Publication number: 20220093483Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.Type: ApplicationFiled: November 30, 2021Publication date: March 24, 2022Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
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Publication number: 20220020846Abstract: In an example, a first hard mask is formed on a first surface of a semiconductor body, wherein first openings in the first hard mask expose first surface sections and second openings in the first hard mask expose second surface sections. First dopants of a first conductivity type are implanted selectively through the first openings into the semiconductor body. Second dopants of a second conductivity type are implanted selectively through the second openings into the semiconductor body. The second conductivity type is complementary to the first conductivity type. A second hard mask is formed that covers the first surface sections and the second surface sections, wherein third openings in the second hard mask expose third surface sections and fourth openings in the second hard mask expose fourth surface sections. Third dopants of the first conductivity type are implanted selectively through the third openings into the semiconductor body.Type: ApplicationFiled: July 13, 2021Publication date: January 20, 2022Inventor: Andreas VOERCKEL
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Patent number: 11217500Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.Type: GrantFiled: April 9, 2019Date of Patent: January 4, 2022Assignee: Infineon Technologies AGInventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
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Publication number: 20200243340Abstract: Forming a semiconductor arrangement includes providing a first semiconductor layer having a first surface, forming a first plurality of trenches in the first surface of the first semiconductor layer, each of the trenches in the first plurality having first and second sidewalls that extend from the first surface to a bottom of the respective trench, implanting first type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, implanting second type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, and annealing the semiconductor arrangement to simultaneously activate the first type dopant atoms and the second type dopant atoms.Type: ApplicationFiled: April 16, 2020Publication date: July 30, 2020Inventors: Anton Mauder, Hans Weber, Franz Hirler, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
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Patent number: 10679855Abstract: Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.Type: GrantFiled: October 12, 2018Date of Patent: June 9, 2020Assignee: Infineon Technologies Austria AGInventors: Anton Mauder, Hans Weber, Franz Hirler, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
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Patent number: 10553681Abstract: A method includes forming first regions of a first doping type and second regions of a second doping type in first and second semiconductor layers such that the first and second regions are arranged alternately in at least one horizontal direction of the first and second semiconductor layers, and forming a control structure with transistor cells each including at least one body region, at least one source region and at least one gate electrode in the second semiconductor layer. Forming the first and second regions includes: forming trenches in the first semiconductor layer and implanting at least one of first and second type dopant atoms into sidewalls of the trenches; forming the second semiconductor layer on the first semiconductor layer such that the second layer fills the trenches; implanting at least one of first and second type dopant atoms into the second semiconductor layer; and at least one temperature process.Type: GrantFiled: August 17, 2018Date of Patent: February 4, 2020Assignee: Infineon Technologies Austria AGInventors: Hans Weber, Franz Hirler, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
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Publication number: 20190311966Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.Type: ApplicationFiled: April 9, 2019Publication date: October 10, 2019Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
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Patent number: 10224394Abstract: According to an embodiment of a semiconductor substrate, the semiconductor substrate includes a superjunction structure in a device region of a semiconductor layer and an alignment mark in a kerf region of the semiconductor layer. The superjunction structure includes first regions and second regions of opposite conductivity types, the first and the second regions alternating along at least one horizontal direction. The alignment mark includes a vertical step formed by an alignment structure projecting or recessed from a main surface of the semiconductor layer. The alignment structure is of a material of the first regions of the superjunction structure.Type: GrantFiled: February 2, 2018Date of Patent: March 5, 2019Assignee: Infineon Technologies Austria AGInventors: Hans Weber, Christian Fachmann, Daniel Tutuc, Andreas Voerckel
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Publication number: 20190058038Abstract: A method includes forming first regions of a first doping type and second regions of a second doping type in first and second semiconductor layers such that the first and second regions are arranged alternately in at least one horizontal direction of the first and second semiconductor layers, and forming a control structure with transistor cells each including at least one body region, at least one source region and at least one gate electrode in the second semiconductor layer. Forming the first and second regions includes: forming trenches in the first semiconductor layer and implanting at least one of first and second type dopant atoms into sidewalls of the trenches; forming the second semiconductor layer on the first semiconductor layer such that the second layer fills the trenches; implanting at least one of first and second type dopant atoms into the second semiconductor layer; and at least one temperature process.Type: ApplicationFiled: August 17, 2018Publication date: February 21, 2019Inventors: Hans Weber, Franz Hirler, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
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Publication number: 20190051529Abstract: Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.Type: ApplicationFiled: October 12, 2018Publication date: February 14, 2019Inventors: Anton Mauder, Hans Weber, Franz Hirler, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
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Patent number: 10134636Abstract: A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first carrier; dicing the semiconductor workpiece and the carrier so as to form at least one individual semiconductor chip; mounting the at least one semiconductor chip with a side facing away from the carrier, to an additional carrier.Type: GrantFiled: November 21, 2017Date of Patent: November 20, 2018Assignee: Infineon Technologies Austria AGInventor: Andreas Voerckel
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Patent number: 10109489Abstract: Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.Type: GrantFiled: July 13, 2017Date of Patent: October 23, 2018Assignee: Infineon Technologies Austria AGInventors: Anton Mauder, Hans Weber, Franz Hirler, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder, Maximilian Treiber, Daniel Tutuc, Andreas Voerckel
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Publication number: 20180158901Abstract: According to an embodiment of a semiconductor substrate, the semiconductor substrate includes a superjunction structure in a device region of a semiconductor layer and an alignment mark in a kerf region of the semiconductor layer. The superjunction structure includes first regions and second regions of opposite conductivity types, the first and the second regions alternating along at least one horizontal direction. The alignment mark includes a vertical step formed by an alignment structure projecting or recessed from a main surface of the semiconductor layer. The alignment structure is of a material of the first regions of the superjunction structure.Type: ApplicationFiled: February 2, 2018Publication date: June 7, 2018Inventors: Hans Weber, Christian Fachmann, Daniel Tutuc, Andreas Voerckel
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Publication number: 20180076090Abstract: A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first carrier; dicing the semiconductor workpiece and the carrier so as to form at least one individual semiconductor chip; mounting the at least one semiconductor chip with a side facing away from the carrier, to an additional carrier.Type: ApplicationFiled: November 21, 2017Publication date: March 15, 2018Inventor: Andreas Voerckel
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Publication number: 20180061979Abstract: A semiconductor device is manufactured in a semiconductor body of a wafer by forming a mask on a surface of the semiconductor body. The mask has a plurality of first mask openings in a transistor cell area and a mask opening design outside the transistor cell area. The mask opening design includes one second mask opening or a plurality of second mask openings encircling the transistor cell area. The plurality of second mask openings are consecutively arranged at lateral distances smaller than a width of the plurality of second mask openings. A plurality of first trenches are formed in the semiconductor body at the first mask openings. One or a plurality of second trenches are formed at the one or plurality of second mask openings. The first trenches and the and one or the plurality of second trenches are filled with a filling material including at least a semiconductor material.Type: ApplicationFiled: August 23, 2017Publication date: March 1, 2018Inventors: Hans Weber, Andreas Voerckel, Franz Hirler, Maximilian Treiber