Abstract: By using a single trench mask, first and second trenches are formed that extend from a main surface into a semiconductor layer. A foundation is formed that includes first regions in and/or directly adjoining the first trenches. A superstructure is formed in alignment with the foundation by using position information directly obtained from structures formed in the first and/or the second trenches.

Abstract: A charge-compensation semiconductor device includes a semiconductor body having a first surface, a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, and a peripheral area arranged between the active area and the lateral edge. A source metallization is arranged on the first surface. A drain metallization is arranged opposite to the source metallization. The semiconductor body further includes a drift region in Ohmic contact with the drain metallization, and a plurality of compensation regions forming respective pn-junctions with the drift region, which are arranged in the active area and in the peripheral area, and are in Ohmic contact with the source metallization via respective body regions arranged in the active area and having a higher doping concentration than the compensation regions.

Abstract: Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.

Abstract: A charge-compensation semiconductor device includes a semiconductor body having a first surface, a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, a peripheral area arranged between the active area and the lateral edge, a drift region, first compensation regions forming respective first pn-junctions with the drift region, and second compensation regions extending from the first surface into the drift region and forming respective second pn-junctions with the drift region. The first compensation regions form in the active area a lattice comprising a first base vector having a first length. The second compensation regions have, in a horizontal direction parallel to the first surface, a horizontal width which decreases with an increasing vertical distance from the first surface and with a decreasing horizontal distance from the edge.

Abstract: A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first carrier; dicing the semiconductor workpiece and the carrier so as to form at least one individual semiconductor chip; mounting the at least one semiconductor chip with a side facing away from the carrier, to an additional carrier.

Abstract: A super-junction semiconductor device includes a junction termination area at a first surface of a semiconductor body and at least partly surrounding an active cell area. An inner part of the junction termination area is arranged between an outer part of the junction termination area and the active cell area. A charge compensation device structure includes first regions of a first conductivity type and second regions of a second conductivity type disposed alternately along a first lateral direction. First surface areas correspond to a projection of the first regions onto the first surface, and second surface areas correspond to a projection of the second regions onto the first surface. The super-junction semiconductor device further includes at least one of a first junction termination extension structure and a second junction termination extension structure.

Abstract: A semiconductor device comprises at least one strip-shaped cell compensation region of a vertical electrical element arrangement, at least one strip-shaped edge compensation region and a bridge structure. The at least one strip-shaped cell compensation regions extends into a semiconductor substrate and comprises a first conductivity type. Further, the at least one strip-shaped cell compensation region is connected to a first electrode structure of the vertical electrical element arrangement. The at least one strip-shaped edge compensation region extends into the semiconductor substrate within an edge termination region of the semiconductor device and outside the cell region. Further, the at least one strip-shaped edge compensation region comprises the first conductivity type. The bridge structure electrically connects the at least one strip-shaped edge compensation region with the at least one strip-shaped cell compensation region within the edge termination region.

Abstract: By using a single trench mask, first and second trenches are formed that extend from a main surface into a semiconductor layer. A foundation is formed that includes first regions in and/or directly adjoining the first trenches. A superstructure is formed in alignment with the foundation by using position information directly obtained from structures formed in the first and/or the second trenches.

Abstract: A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first carrier; dicing the semiconductor workpiece and the carrier so as to form at least one individual semiconductor chip; mounting the at least one semiconductor chip with a side facing away from the carrier, to an additional carrier.

Abstract: A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first carrier; dicing the semiconductor workpiece and the carrier so as to form at least one individual semiconductor chip; mounting the at least one semiconductor chip with a side facing away from the carrier, to an additional carrier.

Abstract: A charge-compensation semiconductor device includes a semiconductor body having a first surface, a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, and a peripheral area arranged between the active area and the lateral edge. A source metallization is arranged on the first surface. A drain metallization is arranged opposite to the source metallization. The semiconductor body further includes a drift region in Ohmic contact with the drain metallization, and a plurality of compensation regions forming respective pn-junctions with the drift region, which are arranged in the active area and in the peripheral area, and are in Ohmic contact with the source metallization via respective body regions arranged in the active area and having a higher doping concentration than the compensation regions.

Abstract: A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first carrier; dicing the semiconductor workpiece and the carrier so as to form at least one individual semiconductor chip; mounting the at least one semiconductor chip with a side facing away from the carrier, to an additional carrier.

Abstract: A super-junction semiconductor device includes a junction termination area at a first surface of a semiconductor body and at least partly surrounding an active cell area. An inner part of the junction termination area is arranged between an outer part of the junction termination area and the active cell area. A charge compensation device structure includes first regions of a first conductivity type and second regions of a second conductivity type disposed alternately along a first lateral direction. First surface areas correspond to a projection of the first regions onto the first surface, and second surface areas correspond to a projection of the second regions onto the first surface. The super-junction semiconductor device further includes at least one of a first junction termination extension structure and a second junction termination extension structure.

Abstract: A charge-compensation semiconductor device includes a semiconductor body having a first surface, a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, and a peripheral area arranged between the active area and the lateral edge. A source metallization is arranged on the first surface. A drain metallization is arranged opposite to the source metallization. The semiconductor body further includes a drift region in Ohmic contact with the drain metallization, and a plurality of compensation regions forming respective pn-junctions with the drift region, which are arranged in the active area and in the peripheral area, and are in Ohmic contact with the source metallization via respective body regions arranged in the active area and having a higher doping concentration than the compensation regions.

Abstract: A semiconductor device comprises at least one strip-shaped cell compensation region of a vertical electrical element arrangement, at least one strip-shaped edge compensation region and a bridge structure. The at least one strip-shaped cell compensation regions extends into a semiconductor substrate and comprises a first conductivity type. Further, the at least one strip-shaped cell compensation region is connected to a first electrode structure of the vertical electrical element arrangement. The at least one strip-shaped edge compensation region extends into the semiconductor substrate within an edge termination region of the semiconductor device and outside the cell region. Further, the at least one strip-shaped edge compensation region comprises the first conductivity type. The bridge structure electrically connects the at least one strip-shaped edge compensation region with the at least one strip-shaped cell compensation region within the edge termination region.

Abstract: A charge-compensation semiconductor device includes a semiconductor body having a first surface, a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, a peripheral area arranged between the active area and the lateral edge, a drift region, first compensation regions forming respective first pn-junctions with the drift region, and second compensation regions extending from the first surface into the drift region and forming respective second pn-junctions with the drift region. The first compensation regions form in the active area a lattice comprising a first base vector having a first length. The second compensation regions have, in a horizontal direction parallel to the first surface, a horizontal width which decreases with an increasing vertical distance from the first surface and with a decreasing horizontal distance from the edge.

Abstract: A charge-compensation semiconductor device includes a semiconductor body having a first surface, a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, and a peripheral area arranged between the active area and the lateral edge. A source metallization is arranged on the first surface. A drain metallization is arranged opposite to the source metallization. The semiconductor body further includes a drift region in Ohmic contact with the drain metallization, and a plurality of compensation regions forming respective pn-junctions with the drift region, which are arranged in the active area and in the peripheral area, and are in Ohmic contact with the source metallization via respective body regions arranged in the active area and having a higher doping concentration than the compensation regions.

Abstract: A semiconductor device according to an embodiment is at least partially arranged in or on a substrate and includes a recess forming a mesa, wherein the mesa extends along a direction into the substrate to a bottom plane of the recess and includes a semiconducting material of a first conductivity type, the semiconducting material of the mesa including at least locally a first doping concentration not extending further into the substrate than the bottom plane. The semiconductor device further includes an electrically conductive structure arranged at least partially along a sidewall of the mesa, the electrically conductive structure forming a Schottky or Schottky-like electrical contact with the semiconducting material of the mesa, wherein the substrate comprises the semiconducting material of the first conductivity type comprising at least locally a second doping concentration different from the first doping concentration along a projection of the mesa into the substrate.

Abstract: A semiconductor device according to an embodiment is at least partially arranged in or on a substrate and includes a recess forming a mesa, wherein the mesa extends along a direction into the substrate to a bottom plane of the recess and includes a semiconducting material of a first conductivity type, the semiconducting material of the mesa including at least locally a first doping concentration not extending further into the substrate than the bottom plane. The semiconductor device further includes an electrically conductive structure arranged at least partially along a sidewall of the mesa, the electrically conductive structure forming a Schottky or Schottky-like electrical contact with the semiconducting material of the mesa, wherein the substrate comprises the semiconducting material of the first conductivity type comprising at least locally a second doping concentration different from the first doping concentration along a projection of the mesa into the substrate.

Abstract: A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first carrier; dicing the semiconductor workpiece and the carrier so as to form at least one individual semiconductor chip; mounting the at least one semiconductor chip with a side facing away from the carrier, to an additional carrier.