Patents by Inventor Andreas Wolter

Andreas Wolter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190341371
    Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.
    Type: Application
    Filed: July 18, 2019
    Publication date: November 7, 2019
    Inventors: Bernd Waidhas, Georg Seidemann, Andreas Augustin, Laurent Millou, Andreas Wolter, Reinhard Mahnkopf, Stephan Stoeckl, Thomas Wagner
  • Publication number: 20190333886
    Abstract: A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.
    Type: Application
    Filed: July 8, 2019
    Publication date: October 31, 2019
    Inventors: Klaus Reingruber, Andreas Wolter, Georg Seidemann, Thomas Wagner, Bernd Waidhas
  • Publication number: 20190304922
    Abstract: A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Inventors: Saravana Maruthamuthu, Thomas Ort, Andreas Wolter, Andreas Augustin, Veronica Sciriha, Bernd Waidhas
  • Patent number: 10431545
    Abstract: A multi-chip module includes two silicon bridge interconnects and three components that are tied together by the bridges with one of the components in the center. At least one of the silicon bridge interconnects is bent to create a non-planar chip-module form factor. Cross-connected multi-chip silicon bent-bridge interconnect modules include the two silicon bridges contacting the center component at right angles to each other, plus a fourth component and a third silicon bridge interconnect contacting the fourth component and any one of the original three components.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: October 1, 2019
    Assignee: Intel IP Corporation
    Inventors: Georg Seidemann, Bernd Waidhas, Thomas Wagner, Andreas Wolter, Laurent Millou
  • Publication number: 20190287904
    Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.
    Type: Application
    Filed: December 29, 2016
    Publication date: September 19, 2019
    Inventors: Georg Seidemann, Thomas Wagner, Andreas Wolter, Bernd Waidhas
  • Patent number: 10411000
    Abstract: A microelectronic package is described with an illuminated backside exterior. In one example, the package has a package substrate, a die attached to the package substrate, a cover over the die and the package substrate, a lamp, and a screen over the die, externally visible and optically coupled to the lamp so that when the lamp is illuminated the illumination is externally visible through the screen.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: September 10, 2019
    Assignee: Intel IP Corporation
    Inventors: Marc Stephan Dittes, Sven Albers, Christian Georg Geissler, Andreas Wolter, Klaus Reingruber, Georg Seidemann, Thomas Wagner, Richard Patten
  • Publication number: 20190272950
    Abstract: A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.
    Type: Application
    Filed: March 2, 2018
    Publication date: September 5, 2019
    Inventors: Saravana Maruthamuthu, Andreas Augustin, Andreas Wolter
  • Patent number: 10403602
    Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 3, 2019
    Assignee: Intel IP Corporation
    Inventors: Bernd Waidhas, Georg Seidemann, Andreas Augustin, Laurent Millou, Andreas Wolter, Reinhard Mahnkopf, Stephan Stoeckl, Thomas Wagner
  • Patent number: 10403609
    Abstract: A system-in-package device includes at least three electrical device components arranged in a common package. A first electrical device component includes a first vertical dimension, a second electrical device component includes a second vertical dimension and a third electrical device component comprises a third vertical dimension. The first electrical device component and the second electrical device component are arranged side by side in the common package. Further, the third electrical device component is arranged on top of the first electrical device component in the common package. At least a part of the third electrical device component is arranged vertically between a front side level of the second electrical device component and a back side level of the second electrical device component.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: September 3, 2019
    Assignee: Intel IP Corporation
    Inventors: Christian Geissler, Sven Albers, Georg Seidemann, Andreas Wolter, Klaus Reingruber, Thomas Wagner, Marc Dittes
  • Patent number: 10373844
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: August 6, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Sven Albers, Sonja Koller, Thorsten Meyer, Georg Seidemann, Christian Geissler, Andreas Wolter
  • Patent number: 10366968
    Abstract: A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: July 30, 2019
    Assignee: Intel IP Corporation
    Inventors: Klaus Reingruber, Andreas Wolter, Georg Seidemann, Thomas Wagner, Bernd Waidhas
  • Publication number: 20190221349
    Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.
    Type: Application
    Filed: March 27, 2019
    Publication date: July 18, 2019
    Inventors: Andreas Wolter, Thorsten Meyer, Gerhard Knoblinger
  • Publication number: 20190214369
    Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing reduced height semiconductor packages for mobile electronics. For instance, there is disclosed in accordance with one embodiment a stacked die package having therein a bottom functional silicon die; a recess formed within the bottom functional silicon die by a thinning etch partially reducing a vertical height of the bottom functional silicon die at the recess; and a top component positioned at least partially within the recess formed within the bottom functional silicon die. Other related embodiments are disclosed.
    Type: Application
    Filed: September 28, 2016
    Publication date: July 11, 2019
    Inventors: Georg SEIDEMANN, Thomas WAGNER, Klaus REINGRUBER, Bernd WAIDHAS, Andreas WOLTER
  • Publication number: 20190214327
    Abstract: A semiconductor device includes a semiconductor die that is coupled to a substrate. A mold compound encapsulates the semiconductor die and one or more passages are in the mold compound between a backside of the mold compound and an electrically non-active region of the first semiconductor die. A thermal conductor material within the one or more of the passages.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Inventors: Sonja Koller, Bernd Waidhas, Thomas Ort, Andreas Wolter
  • Publication number: 20190206833
    Abstract: Embodiments of the invention include an eWLB or ePLB based PoP device and methods of forming such devices. According to an embodiment, such a device may include a die embedded within a mold layer. A substrate may be directly contacting a surface of the mold layer. Additionally, embodiments of the invention may include a through mold via formed through the mold layer that is electrically coupled to a contact formed on a surface of the substrate that is contacting the mold layer. In order to form such a device, embodiments may include dispensing a molding material over a die positioned on a mold carrier. Thereafter, a substrate may be pressed into the molding material. After curing the molding material, a mold layer may be formed that encases the die and is adhered to the substrate.
    Type: Application
    Filed: December 23, 2015
    Publication date: July 4, 2019
    Inventors: Thorsten MEYER, Klaus REINGRUBER, Georg SEIDEMANN, Andreas WOLTER, Christian GEISSLER, Sven ALBERS
  • Patent number: 10319688
    Abstract: An antenna is described on ceramics that may be used for a packaged die. In one example, a package has a die, a ceramic substrate over the die, an antenna attached to the ceramic substrate, and conductive leads electrically connecting the antenna to the die.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Andreas Wolter, Saravana Maruthamuthu, Mikael Knudsen, Thorsten Meyer, Georg Seidemann, Pablo Herrero, Pauli Jaervinen
  • Patent number: 10290412
    Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: May 14, 2019
    Assignee: Intel IP Corporation
    Inventors: Andreas Wolter, Thorsten Meyer, Gerhard Knoblinger
  • Publication number: 20190121041
    Abstract: Embodiments of the disclosure are directed to a chip package that includes a base that includes a redistribution layer; an optical transducer circuit element on the base electrically connected to the redistribution layer; an optical element adjacent to the optical transducer circuit element and at an edge of the base; and an encasement encasing the optical transducer circuit element and a portion of the optical element, wherein one side of the optical element is exposed at an edge of the encasement and at the edge of the printed circuit board.
    Type: Application
    Filed: March 28, 2016
    Publication date: April 25, 2019
    Applicant: Intel IP Corporation
    Inventors: Sven Albers, Marc Dittes, Andreas Wolter, Klaus Reingruber, Georg Seidemann, Christian Geissler, Thomas Wagner, Richard Patten
  • Publication number: 20190103333
    Abstract: A semiconductor device includes a plurality of circuit regions formed at a circuit semiconductor layer of a semiconductor die. The semiconductor device includes an etch stop layer of the semiconductor die arranged between the circuit semiconductor layer of the semiconductor die and a handling layer of the semiconductor die. The semiconductor device includes one or more trench structures extending through the handling layer of the semiconductor die. The one or more trench structures extends to at least the etch stop layer and to at most the circuit semiconductor layer of the semiconductor die.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Reinhard Mahnkopf, Andreas Wolter, Sonja Koller
  • Publication number: 20190103347
    Abstract: A system and method for aligning components is disclosed. A system arranges a plurality of components in a first component alignment. The system places two L-shaped fine placement tools in a position surrounding the plurality of components, wherein the L-shaped fine placement tools include a plurality of pins. The system applies a force to the pins included in the two L-shaped fine placement tools to shift the plurality of components from the first component alignment to a second component alignment, wherein the second component alignment has less unused space than the first component alignment. The system removes the two L-shaped fine placement tools. The system attaches the plurality of components to a carrier arranged in the second component alignment.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Georg Seidemann, Andreas Wolter, Stephan Stoeckl, Thomas Wagner