Abstract: An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure located between the redistribution layer structure and the inter-diffusing material contact structure. The vertical electrically conductive structure includes a diffusion barrier structure located adjacently to the inter-diffusing material contact structure. Further, the diffusion barrier structure and the redistribution layer structure comprise different lateral dimensions.

Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

Abstract: Present disclosure relates to IC devices with thermal mitigation structures in the form of metal structures provided in a semiconductor material of a substrate on which active electronic devices are integrated (i.e., front-end metal structures). In one aspect, an IC device includes a substrate having a first face and a second face, where at least one active electronic device is integrated at the first face of the substrate. The IC device further includes at least one front-end metal structure that extends from the first face of the substrate into the substrate to a depth that is smaller than a distance between the first face and the second face. Providing front-end metal structures may enable improved cooling options because such structures may be placed in closer vicinity to the active electronic devices, compared to conventional thermal mitigation approaches.

Abstract: Embodiments may include an IC having an active substrate containing devices, and a bulk substrate, separated by an oxide layer or an etching stop layer. The IC may be partially thinned from a backside of the bulk substrate to create a cavity, while maintaining the dicing streets and/or the edges of the bulk substrate without being thinned. The cavity may be surrounded by a first edge and a second edge of the bulk substrate. An additional IC may be placed within the cavity of the bulk substrate to form a stacking IC with a reduced height. The ICs of the stacking IC may be electronically coupled using TSVs embedded within the active substrate of the ICs. Other embodiments may be described and/or claimed.

Abstract: A method includes aligning a wire with a package body having a contact pad and moving the wire through the package body to form electrical contact with the contact pad.

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

Abstract: A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.

Abstract: A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.

Abstract: A multi-chip module includes two silicon bridge interconnects and three components that are tied together by the bridges with one of the components in the center. At least one of the silicon bridge interconnects is bent to create a non-planar chip-module form factor. Cross-connected multi-chip silicon bent-bridge interconnect modules include the two silicon bridges contacting the center component at right angles to each other, plus a fourth component and a third silicon bridge interconnect contacting the fourth component and any one of the original three components.

Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.

Abstract: A microelectronic package is described with an illuminated backside exterior. In one example, the package has a package substrate, a die attached to the package substrate, a cover over the die and the package substrate, a lamp, and a screen over the die, externally visible and optically coupled to the lamp so that when the lamp is illuminated the illumination is externally visible through the screen.

Abstract: A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.

Abstract: A system-in-package device includes at least three electrical device components arranged in a common package. A first electrical device component includes a first vertical dimension, a second electrical device component includes a second vertical dimension and a third electrical device component comprises a third vertical dimension. The first electrical device component and the second electrical device component are arranged side by side in the common package. Further, the third electrical device component is arranged on top of the first electrical device component in the common package. At least a part of the third electrical device component is arranged vertically between a front side level of the second electrical device component and a back side level of the second electrical device component.

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

Abstract: A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.

Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing reduced height semiconductor packages for mobile electronics. For instance, there is disclosed in accordance with one embodiment a stacked die package having therein a bottom functional silicon die; a recess formed within the bottom functional silicon die by a thinning etch partially reducing a vertical height of the bottom functional silicon die at the recess; and a top component positioned at least partially within the recess formed within the bottom functional silicon die. Other related embodiments are disclosed.

Abstract: A semiconductor device includes a semiconductor die that is coupled to a substrate. A mold compound encapsulates the semiconductor die and one or more passages are in the mold compound between a backside of the mold compound and an electrically non-active region of the first semiconductor die. A thermal conductor material within the one or more of the passages.

Abstract: Embodiments of the invention include an eWLB or ePLB based PoP device and methods of forming such devices. According to an embodiment, such a device may include a die embedded within a mold layer. A substrate may be directly contacting a surface of the mold layer. Additionally, embodiments of the invention may include a through mold via formed through the mold layer that is electrically coupled to a contact formed on a surface of the substrate that is contacting the mold layer. In order to form such a device, embodiments may include dispensing a molding material over a die positioned on a mold carrier. Thereafter, a substrate may be pressed into the molding material. After curing the molding material, a mold layer may be formed that encases the die and is adhered to the substrate.