Abstract: A short gate high power metal oxide semiconductor field effect transistor formed in a trench includes a short gate having gate length defined by spacers within the trench. The transistor further includes a buried region that extends beneath the trench and beyond a corner of the trench, that effectively shields the gate from high drain voltage, to prevent short channel effects and resultantly improve device performance and reliability.

Abstract: A trench metal oxide semiconductor field effect transistor or UMOSFET, includes a buried region that extends beneath the trench and beyond a corner of the trench. The buried region is tied to a source potential of the UMOSFET, and splits the potential realized across the structure. This effectively shields the electric field from the corners of the trench to reduce gate oxide stress, and resultantly improves device performance and reliability.

Abstract: A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.

Abstract: A vertical junction field effect transistor includes a trench formed in an epitaxial layer. The trench surrounds a channel region of the epitaxial layer. The channel region may have a graded or uniform dopant concentration profile. An epitaxial gate structure is formed within the trench by epitaxial regrowth. The epitaxial gate structure may include separate first and second epitaxial gate layers, and may have either a graded or uniform dopant concentration profile.

Abstract: A lateral field effect transistor for high switching frequencies having a source region layer (4) and a drain region layer (5) laterally spaced and of highly doped first conductivity type, a first-conductivity-type channel layer (6) of lower doping concentration extending laterally and interconnecting the source region layer (4) and the drain region layer (5). The transistor has a gate electrode (7) arranged to control the properties of the channel layer (6), and a highly doped second-conductivity-type base layer (8) arranged under the channel layer (6) at least partially overlapping the gate electrode (7) and at a lateral distance to the drain region layer (5), the highly doped second-conductivity-type base layer (8) being shorted to the source region layer (4).

Abstract: A vertical junction field effect transistor includes a trench formed in an epitaxial layer. The trench surrounds a channel region of the epitaxial layer. The channel region may have a graded or uniform dopant concentration profile. An epitaxial gate structure is formed within the trench by epitaxial regrowth. The epitaxial gate structure may include separate first and second epitaxial gate layers, and may have either a graded or uniform dopant concentration profile.

Abstract: Method for producing a field effect transistor having a source region (9), a drain region and a channel layer (11) interconnecting the source and drain regions, and including the step of providing a sacrificial layer (4) on part of a semiconductor material (1) whose edge is used to define the edge of an implant, such as the source region (9), in the semiconductor material (1), where the edge (4c) of the sacrificial layer (4) is subsequently used to define the edge of a gate (16).

Abstract: A vertical junction field effect transistor includes a trench formed in an epitaxial layer. The trench surrounds a channel region of the epitaxial layer. The channel region may have a graded or uniform dopant concentration profile. An epitaxial gate structure is formed within the trench by epitaxial regrowth. The epitaxial gate structure may include separate first and second epitaxial gate layers, and may have either a graded or uniform dopant concentration profile.

Abstract: A vertical junction field effect transistor includes a trench formed in an epitaxial layer. The trench surrounds a channel region of the epitaxial layer. The channel region may have a graded or uniform dopant concentration profile. An epitaxial gate structure is formed within the trench by epitaxial regrowth. The epitaxial gate structure may include separate first and second epitaxial gate layers, and may have either a graded or uniform dopant concentration profile.

Abstract: The invention relates to a method for selective etching of SiC, the etching being carried out by applying a positive potential to a layer (3; 8) of p-type SiC being in contact with an etching solution containing fluorine ions and having an oxidising effect on SiC. The invention also relates to a method for producing a SiC micro structure having free hanging parts (i.e. diaphragm, cantilever or beam) on a SiC-substrate, a method for producing a MEMS device of SiC having a free hanging structure, and a method for producing a piezo-resistive pressure sensor comprising the step of applying a positive potential to a layer (8) of p-type SiC being in contact with an etching solution containing fluorine ions and having an oxidising effect on SiC.

Abstract: A field effect transistor of SiC for high temperature application has the source region layer (4), the drain region layer (5) and the channel region layer (6, 7) vertically separated from a front surface (14), where a gate electrode (12) is arranged, for reducing the electric field at said surface in operation of the transistor and in the case of operation as a gas sensor permitting all electrodes except for the gate electrode to be protected from the atmosphere.

Abstract: In a high power IMPATT ( Impact Avalanche Transit Time) diode for generating high frequency signals two electrodes, anode (2) and cathode (1), are arranged with a semiconductor layer therebetween. Said semiconductor layer comprises a drift layer (7) for transport of charge carriers between the electrodes. The semiconductor layer is made of crystalline SiC and it is provided with means (9) adapted to locally increase the electric field in the drift layer substantially with respect to the average electric field therein for generating an avalanche breakdown at a considerably lower voltage across the electrodes than would the electric field be substantially constant across the entire drift layer.

Abstract: A lateral field effect transistor of SiC for high switching frequencies comprises a source region layer (5) and a drain region layer (6) laterally spaced and highly doped n-type, an n-type channel layer (4) extending laterally and interconnecting the source region layer and the drain region layer for conducting a current between these layers in the on-state of the transistor, and a gate electrode (9) arranged to control the channel layer to be conducting or blocking through varying the potential applied to the gate electrode. A highly doped p-type base layer (12) is arranged next to the channel layer at least partially overlapping the gate electrode and being at a lateral distance to the drain region layer. The base layer is shorted to the source region layer.

Abstract: A method of fabricating a semiconductor device on a substrate, wherein the substrate comprises a first layer of doped silicon carbide of a first conducting type and exhibits at least one hollow defect. In a first step the positions of the hollow defects in the substrate are identified, whereafter a second SiC layer of a second conducting type is formed in contact with the first layer, whereafter the first and second layer constituting the pn junction are provided with at least one edge termination surrounding any hollow defect, whereby the defect is excluded from the high-field region of the device.

Abstract: A method for introducing an impurity dopant into a semiconductor layer of SiC is provided. Ions are implanted into the semiconductor layer so that a near surface of the semiconductor layer becomes doped and amorphous. The semiconductor layer is then annealed at a temperature so that the dopant diffuses into a non-implanted sublayer of the semiconductor layer below the near surface layer.

Abstract: A semiconductor device comprises a semiconductor layer of SiC and an insulating layer thereon for insulating the SiC layer with respect to a metal plate constituting a gate and connectable to a voltage for creating a conducting surface channel at a SiC layer-insulating layer interface, wherein at least a portion of the insulating layer closest to the interface is made of a crystalline material which is substantially lattice-matched to SiC and has substantially the same coefficient of thermal expansion as SiC; and wherein the material has AlN as the only component or as a major component of an alloy with insulating properties.

Abstract: A method for introduction of an impurity dopant into a semiconductor layer of SiC comprises the step of ion implantation of the dopant in the semiconductor layer at a low temperature. The ion implantation is carried out in such a way that a doped and amorphous near-surface layer is formed, and the implantation step is followed by a step of annealing the semiconductor layer at such a high temperature that the dopant diffuses into the non-implanted sub-layer of the semiconductor layer following the near-surface layer.

Abstract: A transistor of SiC having an insulated gate comprises a drain contact with a highly doped substrate layer formed on the drain. The substrate layer is of p-type or of n-type. For a p-type transistor, a highly doped n-type buffer layer may optionally be formed on top of the substrate layer. A low doped n-type drift layer, a highly doped p-type base layer, a highly doped n-type source region, and a source contact are then superimposed on the substrate layer. A vertical trench extends through the source region and the base layer to at least the drift layer. The trench has a wall next to these layers. A gate electrode extends vertically along the wall and at least over a vertical extension of the base layer. An insulating layer is arranged between the gate electrode and at least the base layer whereby an inversion channel is formed for electron transport from the source contact to the drain contact.

Abstract: A method for producing a semiconductor device, having a semiconductor layer of a SiC comprises the steps of a) supplying dopants to the surface of the SiC layer during heating thereof for diffusion of the dopants into the SiC layer, and b) highly doping at least a portion of the surface layer of the SiC layer prior to step a) to control diffusion of the dopants into the SiC layer under the surface layer portion.

Abstract: The present invention relates to a method for producing a semiconductor device having a semiconductor layer of SiC. The method comprises the steps of a) applying a mask on at least a portion of the SiC layer to coat a first portion of the SiC layer leaving a second portion thereof uncoated, b) applying a heat treatment to the SiC layer, and c) supplying dopants to the SiC layer during the heat treatment for diffusion of the dopants into the SiC layer at the second portion thereof for doping the SiC layer. The mask is made of crystalline AIN as the only component or AIN as a major component of a crystalline alloy constituting the material.