Patents by Inventor Andrei Papou

Andrei Papou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10957820
    Abstract: A light-emitting device is disclosed which includes a segmented active layer disposed between a segmented conductivity layer and a continuous conductivity layer, the active layer, the segmented conductivity layer, and the continuous conductivity layer being arranged to define a plurality of pixels, each pixel including a different segment of the segmented conductivity layer and the segmented active layer. A continuous wavelength converting layer disposed on the continuous conductivity layer is provided. A plurality of first contacts, each first contact being electrically connected to a different segment of the segmented conductivity layer is provided. One or more second contacts that are electrically connected to the continuous conductivity layer are also provided, the number of second contacts being less than the number of first contacts.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: March 23, 2021
    Assignee: Lumileds LLC
    Inventors: Luke Gordon, Oleg Shchekin, Ashish Tandon, Rajat Sharma, Joseph Flemish, Andrei Papou, Wen Yu, Erik Young
  • Patent number: 10665735
    Abstract: A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where the external temperature can drop to ?40° C., while at the same time maintaining the temperature required for the proper operation of the VCSEL and the gas within the vapor cell.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: May 26, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Peter J. Hopper, William French, Paul Mawson, Steven Hunt, Roozbeh Parsa, Martin Fallon, Ann Gabrys, Andrei Papou
  • Publication number: 20190198564
    Abstract: A device may include a metal contact between a first isolation region and a second isolation region on a first surface of an epitaxial layer. The device may include a first sidewall and a second sidewall on a second surface of the epitaxial layer distal to the first isolation region and the second isolation region. The device may include a wavelength converting layer on the epitaxial layer between the first sidewall and the second sidewall.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 27, 2019
    Applicant: Lumileds LLC
    Inventors: Ashish TANDON, Rajat SHARMA, Joseph Robert FLEMISH, Andrei PAPOU, Wen YU, Erik YOUNG, Yu-Chen SHEN, Luke GORDON
  • Publication number: 20190198716
    Abstract: A light-emitting device is disclosed which includes a segmented active layer disposed between a segmented conductivity layer and a continuous conductivity layer, the active layer, the segmented conductivity layer, and the continuous conductivity layer being arranged to define a plurality of pixels, each pixel including a different segment of the segmented conductivity layer and the segmented active layer. A continuous wavelength converting layer disposed on the continuous conductivity layer is provided. A plurality of first contacts, each first contact being electrically connected to a different segment of the segmented conductivity layer is provided. One or more second contacts that are electrically connected to the continuous conductivity layer are also provided, the number of second contacts being less than the number of first contacts.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 27, 2019
    Applicant: Lumileds LLC
    Inventors: Luke GORDON, Oleg SHCHEKIN, Ashish TANDON, Rajat SHARMA, Joseph FLEMISH, Andrei PAPOU, Wen YU, Erik YOUNG
  • Publication number: 20190189682
    Abstract: A light emitting diode (LED) array may include an epitaxial layer comprising a first pixel and a second pixel separated by an isolation region. A reflective layer may be formed on the epitaxial layer. A p-type contact layer may be formed on the reflective layer. The isolation region may have a width that is at least a width of a trench formed in a p-type contact layer.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 20, 2019
    Applicant: Lumileds LLC
    Inventors: Erik YOUNG, Joseph Robert FLEMISH, Ashish TANDON, Rajat SHARMA, Andrei PAPOU, Wen YU, Yu-Chen SHEN, Luke GORDON
  • Publication number: 20150340422
    Abstract: A method of manufacturing an inductor on a wafer level process that can operate at 20 MHz with good efficiency and a high inductance density is disclosed, wherein the inductor design allows high frequency operation, low RDSON values and high efficiency.
    Type: Application
    Filed: May 23, 2014
    Publication date: November 26, 2015
    Inventors: Dok Won Lee, William D. French, Andrei Papou
  • Publication number: 20150311355
    Abstract: A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where the external temperature can drop to ?40° C., while at the same time maintaining the temperature required for the proper operation of the VCSEL and the gas within the vapor cell.
    Type: Application
    Filed: May 4, 2015
    Publication date: October 29, 2015
    Inventors: Peter J. Hopper, William French, Paul Mawson, Steven Hunt, Roozbeh Parsa, Martin Fallon, Ann Gabrys, Andrei Papou
  • Patent number: 9121106
    Abstract: A laminated magnetic core, which has a number of magnetic layers and a number of insulation layers which are arranged so that an insulation layer lies between each vertically adjacent pair of magnetic layers, is formed in a method that forms the magnetic layers with an electroplating process, and the insulation layers with a sputter depositing process.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: September 1, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dok Won Lee, Andrei Papou, William French, Peter J. Hopper
  • Patent number: 9024397
    Abstract: A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where the external temperature can drop to ?40° C., while at the same time maintaining the temperature required for the proper operation of the VCSEL and the gas within the vapor cell.
    Type: Grant
    Filed: January 7, 2012
    Date of Patent: May 5, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Peter J. Hopper, William French, Paul Mawson, Steven Hunt, Roozbeh Parsa, Martin Fallon, Ann Gabrys, Andrei Papou
  • Patent number: 8531002
    Abstract: An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: September 10, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Andrei Papou
  • Publication number: 20130224887
    Abstract: A laminated magnetic core, which has a number of magnetic layers and a number of insulation layers which are arranged so that an insulation layer lies between each vertically adjacent pair of magnetic layers, is formed in a method that forms the magnetic layers with an electroplating process, and the insulation layers with a sputter depositing process.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 29, 2013
    Inventors: Dok Won Lee, Andrei Papou, William French, Peter J. Hopper
  • Publication number: 20130176703
    Abstract: A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where the external temperature can drop to ?40° C., while at the same time maintaining the temperature required for the proper operation of the VCSEL and the gas within the vapor cell.
    Type: Application
    Filed: January 7, 2012
    Publication date: July 11, 2013
    Inventors: Peter J. Hopper, William French, Paul Mawson, Steven Hunt, Roozbeh Parsa, Martin Fallon, Ann Gabrys, Andrei Papou
  • Publication number: 20130168808
    Abstract: Magnetic laminations are formed in the openings of a first non-conductive structure, which is formed in the opening of a second non-conductive structure that has a maximum aspect ratio that is less than the maximum aspect ratio of the first non-conductive structure. The second non-conductive structure is more crack resistant than the first non-conductive structure, and thereby protects the first non-conductive structure and the magnetic laminations from environmental contaminants.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Inventors: Andrei Papou, William French, Peter J. Hopper
  • Patent number: 8466537
    Abstract: Magnetic laminations are formed in the openings of a first non-conductive structure, which is formed in the opening of a second non-conductive structure that has a maximum aspect ratio that is less than the maximum aspect ratio of the first non-conductive structure. The second non-conductive structure is more crack resistant than the first non-conductive structure, and thereby protects the first non-conductive structure and the magnetic laminations from environmental contaminants.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: June 18, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Andrei Papou, William French, Peter J. Hopper
  • Patent number: 8450830
    Abstract: A plurality of sequential electro-deposition, planarization and insulator deposition steps are performed over a patterned thick photoresist film to form a laminated ferromagnetic alloy core for micro-fabricated inductors and transformers. The use of a plurality of contiguous thin laminations within deep patterns on non-removable photoresist film provides sufficient volume of magnetic film in, for example, high frequency applications, and reduces eddy current loss at high frequency.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: May 28, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, William French, Andrei Papou, Dok Won Lee
  • Patent number: 8410576
    Abstract: An inductor is formed on a wafer by attaching a first core structure to the wafer with a pick and place operation, forming a coil with one or more thick metal layers over the first core structure, and then attaching a second core structure to the first core structure with the pick and place operation after the coil has been formed. In addition, the pick and place operation can also be used to attach one or more integrated circuits to the wafer to form an integrated inductive device.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: April 2, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Peter Smeys, Andrei Papou
  • Patent number: 8407883
    Abstract: A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis is enhanced by electroplating in an applied magnetic field parallel to the easy axis.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: April 2, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Peter Smeys, Peter Johnson, Andrei Papou
  • Publication number: 20130062725
    Abstract: A galvanic isolation system provides galvanic isolation in digital transfer integrated circuits by using conductivity modulation of the semiconductor substrate. Modulation of the conductivity of the substrate affects eddy current losses of a (differential) RF inductor that is isolated from the substrate by a sufficient amount of dielectric material, which provides a basis for signal transfer from the modulated substrate to the inductor across the isolation barrier.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 14, 2013
    Inventors: Peter J. Hopper, Peter Smeys, William French, Andrei Papou, Chaudhuri Dutt Adilti
  • Publication number: 20130062729
    Abstract: A plurality of sequential electro-deposition, planarization and insulator deposition steps are performed over a patterned thick photoresist film to form a laminated ferromagnetic alloy core for micro-fabricated inductors and transformers. The use of a plurality of contiguous thin laminations within deep patterns on non-removable photoresist film provides sufficient volume of magnetic film in, for example, high frequency applications, and reduces eddy current loss at high frequency.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 14, 2013
    Inventors: Peter J. Hopper, William French, Andrei Papou, Dok Won Lee
  • Patent number: 8390093
    Abstract: A galvanic isolation system provides galvanic isolation in digital transfer integrated circuits by using conductivity modulation of the semiconductor substrate. Modulation of the conductivity of the substrate affects eddy current losses of a (differential) RF inductor that is isolated from the substrate by a sufficient amount of dielectric material, which provides a basis for signal transfer from the modulated substrate to the inductor across the isolation barrier.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: March 5, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Smeys, William French, Andrei Papou, Aditi Dutt Chaudhuri