Abstract: An RF front-end receiver comprises a low noise amplifier and a local oscillator driver, which are connected to respective input ports of a mixer which comprises a first and second transistor with gates coupled to one output terminal, a third and fourth transistor with gates coupled to the other output terminal, a fifth and sixth transistor with gates coupled to respective output terminal of the local oscillator driver, the sources of the first and third transistors coupled to the drain of the fifth transistor, the sources of the second and fourth transistor coupled to the drain of the sixth transistor, the sources of the fifth and sixth transistor coupled to ground, the drains of the first and fourth transistor coupled to one output terminal of a mixer output port, and the drains of the second and third transistor coupled to the other output terminal of the mixer output port.

Abstract: A device for ESD (electrostatic discharge) protection of a circuit of a semiconductor device comprises a field effect transistor based varistor with gate, source and drain regions, wherein one of the source and drain regions is connected to an input/output pad of the semiconductor device, and the other one of the source and drain regions is connected to an input/output terminal of the circuit. A biasing circuit is connected to the gate region of the varistor to create an accumulation region below the gate of the varistor at normal operating voltages of said semiconductor device. The semiconductor device is preferably an integrated device on a single substrate.

Abstract: The present invention relates to a cascode radio frequency power amplifier, including at least two cascaded MOS transistors formed in a mutual substrate, where the bulk nodes of the transistors are isolated from each other and connected to the respective source of each transistor. The present invention also teaches that the drain of the topmost transistor is connected to the power supply through an inductive load, and that the gate of each upper transistor is equipped with a self-biasing circuit connected at least between the drain and the gate of the respective upper transistor.

Abstract: A device for ESD protection of a high frequency circuit (1) of a semiconductor device comprises first (3) and second (4) p-type and first (6) and second (5) n-type JFET's, wherein the first p-type JFET (3) is connected with its gate to a high voltage source, its source to an input/output pad (2) of the semiconductor device, and its drain to the source of the first n-type JFET (6), the second p-type JFET (4) is connected with its gate to the high voltage source, its source to the drain of the second n-type JFET (5), and its drain to an input/output terminal of the circuit (1), the first n-type JFET transistor (6) is connected with its gate to ground (GND), and its drain to the input/output terminal, and the second n-type JFET transistor (5) is connected with its gate to ground (GND), and its source to the input/output pad (2).

Abstract: A monolithically integrated microwave amplifier device, comprises an input for receiving a microwave signal, a first power amplifier stage (11; 32) having an input coupled to receive the microwave signal, an impedance matching network (16; 39) coupled to an output of the first power amplifier stage, a second power amplifier stage (12; 33) having an input coupled to the impedance matching network, and an output for outputting the microwave signal after having been amplified by the first and second power amplifier stages, wherein the first power amplifier stage is optimized to be supplied with a first supply voltage (13; 35), which is essentially lower than a second supply voltage (14; 36), with which the second power amplifier stage is optimized to be supplied. Preferably, the second stage is an end stage based on an LDMOS transistor, and the first stage is a driver stage based on a bipolar transistor.

Abstract: To protect a high-frequency integrated circuit (1) against higher voltages than normal operating voltages on an input/output terminal connected to a bonding pad (2), a semiconductor varistor (3) having low and essentially constant resistance for said normal operating voltages and higher resistance for said higher voltages is integrated between the bonding pad (2) and the input/output terminal together with the integrated circuit (1).

Abstract: A device for ESD (electrostatic discharge) protection of a circuit of a semiconductor device comprises a field effect transistor based varistor with gate, source and drain regions, wherein one of the source and drain regions is connected to an input/output pad of the semiconductor device, and the other one of the source and drain regions is connected to an input/output terminal of the circuit. A biasing circuit is connected to the gate region of the varistor to create an accumulation region below the gate of the varistor at normal operating voltages of said semiconductor device. The semiconductor device is preferably an integrated device on a single substrate.

Abstract: An RF front-end receiver comprises a low noise amplifier and a local oscillator driver, which are connected to respective input ports of a mixer which comprises a first and second transistor with gates coupled to one output terminal, a third and fourth transistor with gates coupled to the other output terminal, a fifth and sixth transistor with gates coupled to respective output terminal of the local oscillator driver, the sources of the first and third transistors coupled to the drain of the fifth transistor, the sources of the second and fourth transistor coupled to the drain of the sixth transistor, the sources of the fifth and sixth transistor coupled to ground, the drains of the first and fourth transistor coupled to one output terminal of a mixer output port, and the drains of the second and third transistor coupled to the other output terminal of the mixer output port.

Abstract: A digital radio transceiver integrated circuit includes MOS transistors with normal threshold voltages in the digital circuits, and with reduced threshold voltages in at least some of the analog RF components. This allows the transceiver to be reduced in size and weight, without requiring performance to be compromised.

Abstract: A monolithically integrated MOS varactor switch device comprises an SOI (Silicon-an-Insulator) substrate, a gate on top of the SOI substrate, contact regions in the substrate at each side of the gate, and a well region arranged beneath the gate, wherein the gate includes a gate semiconductor layer region on top of a gate insulation layer region, and the well region interconnects the contact regions. According to the invention the contact regions are laterally separated from the gate, preferably by a distance of at least 10 nm. The contact regions as well as the well region are doped to the same doping type, and the SOI substrate is advantageously thinner than about 200 nm to allow full depletion of the silicon during use of the MOS varactor switch device.

Abstract: A method in the fabrication of an integrated high frequency circuit including a DMOS transistor device comprises the steps of providing a substrate, etching a trench in a region defined for an extended drain for the DMOS transistor, and doping a region below the trench and a region at a side of the trench to a first doping type by means of ion implantation in the etched open trench through a mask, wherein the ion implantation is effectuated in a direction, which is inclined at an angle to the normal of the surface of the substrate, to thereby create a partly lateral and partly vertical current path in the extended drain. The method comprises further the steps of filling the trench with an insulating material to form a shallow trench isolation region, and forming a gate, a channel region, a source, and a drain for the DMOS transistor.

Abstract: To reduce current density in a transistor in an IC comprising a plurality of interdigitated drain, source and gate fingers (10, 11, 12) a first current distributing plate (1) is part of a metal layer of the IC and is connected by first vias (5) to all drain fingers (10) and a second current distributing plate (2) is also part of the metal layer of the IC and is connected by second vias (6) to all source fingers (11).

Abstract: A monolithically integrated vertical DMOS transistor device comprises a semiconductor substrate (11), a gate including a gate semiconductor layer region (27) on top of a gate insulation layer region (25), a source (31), a drain including a buried drain region (13) and a drain contact (21), and a channel region (29) arranged beneath the gate region. The drain comprises a lightly doped, preferably retrograde doped, drain region (23) arranged between the gate and the buried drain region, and the source (31), the channel region (29) and the lightly doped drain region (23) are arranged in a doped well region (17), wherein the lightly doped drain region has a higher doping level than the well region to thereby enhance the high frequency properties of the vertical DMOS transistor device.

Abstract: A monolithically integrated microwave amplifier device, comprises an input for receiving a microwave signal, a first power amplifier stage (11; 32) having an input coupled to receive the microwave signal, an impedance matching network (16; 39) coupled to an output of the first power amplifier stage, a second power amplifier stage (12; 33) having an input coupled to the impedance matching network, and an output for outputting the microwave signal after having been amplified by the first and second power amplifier stages, wherein the first power amplifier stage is optimized to be supplied with a first supply voltage (13; 35), which is essentially lower than a second supply voltage (14; 36), with which the second power amplifier stage is optimized to be supplied. Preferably, the second stage is an end stage based on an LDMOS transistor, and the first stage is a driver stage based on a bipolar transistor.

Abstract: A device for ESD protection of a high frequency circuit (1) of a semiconductor device comprises first (3) and second (4) p-type and first (6) and second (5) n-type JFET's, wherein the first p-type JFET (3) is connected with its gate to a high voltage source, its source to an input/output pad (2) of the semiconductor device, and its drain to the source of the first n-type JFET (6), the second p-type JFET (4) is connected with its gate to the high voltage source, its source to the drain of the second n-type JFET (5), and its drain to an input/output terminal of the circuit (1), the first n-type JFET transistor (6) is connected with its gate to ground (GND), and its drain to the input/output terminal, and the second n-type JFET transistor (5) is connected with its gate to ground (GND), and its source to the input/output pad (2).

Abstract: An array of nanometric dimensions consisting of two or more arms, positioned side by side, wherein the arms are of such nanometric dimensions that the beams can be moved or deformed towards or away from one another by means of a low voltage applied between the beams, whereby to produce a desired optical, electronic or mechanical effect. At nanometer scale dimensions structures previously treated as rigid become flexible, and this flexibility can be engineered since it is a direct consequence of material and dimensions. Since the electrostatic force between the two arms is inversely proportional to the square of the distance, a very considerable force will be developed with a low voltage of the order of 1-5 volts, which is sufficient to deflect the elements towards or away from one another.

Abstract: To protect a high-frequency integrated circuit (1) against higher voltages than normal operating voltages on an input/output terminal connected to a bonding pad (2), a semiconductor varistor (3) having low and essentially constant resistance for said normal operating voltages and higher resistance for said higher voltages is integrated between the bonding pad (2) and the input/output terminal together with the integrated circuit (1).

Abstract: The invention relates to a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, in an n-well CMOS process by adding solely two additional process steps to a conventional CMOS process: (i) a masking step, and (ii) an ion implantation step for forming a doped channel region for the high voltage MOS transistor in the substrate self-aligned to the edge of the high voltage MOS transistor gate region. The ion implantation is performed through the mask in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create the doped channel region partly underneath the gate region of the high voltage MOS transistor.

Abstract: A digital radio transceiver integrated circuit includes MOS transistors with normal threshold voltages in the digital circuits, and with reduced threshold voltages in at least some of the analog RF components. This allows the transceiver to be reduced in size and weight, without requiring performance to be compromised.

Abstract: An array of nanometric dimensions consisting of two or more arms, positioned side by side, wherein the arms are of such nanometric dimensions that the beams can be moved or deformed towards or away from one another by means of a low voltage applied between the beams, whereby to produce a desired optical, electronic or mechanical effect. At nanometer scale dimensions structures previously treated as rigid become flexible, and this flexibility can be engineered since it is a direct consequence of material and dimensions. Since the electrostatic force between the two arms is inversely proportional to the square of the distance, a very considerable force will be developed with a low voltage of the order of 1-5 volts, which is sufficient to deflect the elements towards or away from one another.