Abstract: A digital radio transceiver integrated circuit includes MOS transistors with normal threshold voltages in the digital circuits, and with reduced threshold voltages in at least some of the analog RF components. This allows the transceiver to be reduced in size and weight, without requiring performance to be compromised.

Abstract: A method is disclosed for noise distribution in high resistivity substrates containing differential or balanced integrated circuitry obtaining a noise suppression by an introduction of noise distributors. Noise from an external noise source (5) is made isotropic in relation to branches of a differential or balanced integrated circuitry by creating a low resistivity path adjacent to the differential or balanced integrated circuitry typically formed by two integrated transistors (A, B) or group of transistors. The low resistivity path in the general case is made symmetrical in relation to the integrated transistors thereby forming a noise distributor for distributing the noise evenly. The noise distributor then is formed as a floating substrate contact (10) of the same doping kind as a substrate or a well within which the differential or balanced circuitry is contained.

Abstract: A digital radio transceiver integrated circuit includes MOS transistors with normal threshold voltages in the digital circuits, and with reduced threshold voltages in at least some of the analog RF components. This allows the transceiver to be reduced in size and weight, without requiring performance to be compromised.

Abstract: A field effect transistor is made on a chip comprising a SiC-substrate. The transistor includes a plurality of densely stacked parallel transistor cells occupying totally a rectangular area. Each transistor cell has parallel strip-shaped regions forming the electrodes and active areas of the cell and each inner cell shares its drain and sources electrodes with neighbouring cells. In order to give a good power dissipation allowing an electrical high power of the transistor, the rectangular area has a very elongated shape and specifically it should have a width not larger than substantially 50 &mgr;m. In the rectangular area all the transistor cells have their strip-shaped regions located in parallel to short sides of the rectangular area and are generally very short considering the length of the rectangular area. Thus specifically also each cell has a length not larger than substantially 50 &mgr;m.

Abstract: A silicon substrate material based on silicon has a semi-insulating interior layer isolating the bulk of the substrate material from the top layers, where integrated circuits are to be built. The semi-insulating layer is created by producing submicron particles having Schotty barriers or pn-hereto-barriers and distributing X particles so that the depletion regions then produced around neighbouring particles overlap. Such particles will then deplete the silicon material from electric charge carriers. The substrate material can then be processed using the standard silicon processing methods and allows integrated circuits to be manufactured which are suitable for high frequency applications. A silicon substrate is made by sputtering a metal such as Co in a silicon wafer and then silicidizing the sputtered Co atoms by means of an annealing treatment. A top silicon wafer having a silicon dioxide layer at its bottom surface is then bonded to the sputted layer.

Abstract: The invention relates to a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, in an n-well CMOS process by adding solely two additional process steps to a conventional CMOS process: (i) a masking step, and (ii) an ion implantation step for forming a doped channel region for the high voltage MOS transistor in the substrate self-aligned to the edge of the high voltage MOS transistor gate region. The ion implantation is performed through the mask in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create the doped channel region partly underneath the gate region of the high voltage MOS transistor.

Abstract: The present invention relates to a method and device for interconnecting radio frequency power SiC field effect transistors. To improve the parasitic source inductance advantage is taken of the small size of the transistors, wherein the bonding pads are placed on both sides of the die in such a way that most of the source bonding wires (6) go perpendicularly to the gate and drain bonding wires (7, 8). Multiple bonding wires can be connected to the source bonding pads, reducing the source inductance. An additional advantage comes from such arrangement by reducing the mutual inductance between source/gate and between source/drain due to the orthogonal wire placement.

Abstract: A method is disclosed for noise distribution in high resistivity substrates containing differential or balanced integrated circuitry obtaining a noise suppression by an introduction of noise distributors. Noise from an external noise source (5) is made isotropic in relation to branches of a differential or balanced integrated circuitry by creating a low resistivity path adjacent to the differential or balanced integrated circuitry typically formed by two integrated transistors (A, B) or group of transistors. The low resistivity path in the general case is made symmetrical in relation to the integrated transistors thereby forming a noise distributor for distributing the noise evenly. The noise distributor then is formed as a floating substrate contact (10) of the same doping kind as a substrate or a well within which the differential or balanced circuitry is contained.

Abstract: A field effect transistor is made on a chip comprising a SiC-substrate. The transistor includes a plurality of densely stacked parallel transistor cells occupying totally a rectangular area. Each transistor cell has parallel strip-shaped regions forming the electrodes and active areas of the cell and each inner cell shares its drain and sources electrodes with neighboring cells. In order to give a good power dissipation allowing an electrical high power of the transistor, the rectangular area has a very elongated shape and specifically it should have a width not larger than substantially 50 &mgr;m. In the rectangular area all the transistor cells have their strip-shaped regions located in parallel to short sides of the rectangular area and are generally very short considering the length of the rectangular area. Thus specifically also each cell has a length not larger than substantially 50 &mgr;m.

Abstract: Lower reflow temperature in dielectrics is obtained by using a composite dielectric film. The composite dielectric film includes a first layer doped in the conventional range. A borophosphosilicate glass (BPSG) thick layer having concentrations of around 4.4 wt. % boron and around 5.6 wt. % phosphorus is exemplary. The composite dielectric film includes a second layer doped excessively. A BPSG thin layer having concentrations between 1-4 wt. % phosphorus and between 7-8 wt. % boron is exemplary. A capping layer of conventional dopant concentration may be additionally added to prevent outdiffusion. A composite dielectric BPSG film can be reflowed around 700° C. as compared to the typical 800-900° C. range. After reflow, etching away the second highly doped layer removes any potential adverse effects.

Abstract: A semiconductor integrated circuit comprises a substrate (1) of a first conduction type semiconductor material, an epitaxial layer (10) which is carried by the substrate (1) and which is of a second conduction type semiconductor material different to the first conduction type material, a well (3) of semiconductor material in the epitaxial layer and a semiconductor material, the epitaxial layer (10) being substantially depleted of charges is a region substantially beneath the well (3).

Abstract: A silicon substrate material based on silicon has a semi-insulating interior layer isolating the bulk of the substrate material from the top layers, where integrated circuits are to be built. The semi-insulating layer is created by producing submicron particles having Schottky barriers or pn-hetero-barriers and distributing the particles so that the depletion regions then produced around neighboring particles overlap. Such particles will then deplete the silicon material from electric charge carriers. The substrate material can then be processed using the standard silicon processing methods and allows integrated circuits to be manufactured which are suitable for high frequency applications. A silicon substrate is made by sputtering a metal such as Co in a silicon wafer and then silicidizing sputtered Co atoms by means of an annealing treatment. A top silicon wafer having a silicon dioxide layer at its bottom surface is then bonded to the sputtered layer.

Abstract: A silicon substrate material based on silicon has a semi-insulating interior layer isolating the bulk of the substrate material from the top layers, where integrated circuits are to be built. The semi-insulating layer is created by producing submicron particles having Schottky barriers or pn-hetero-barriers and distributing the particles so that the depletion regions then produced around neighbouring particles overlap. Such particles will then deplete the silicon material from electric charge carriers. The substrate material can then be processed using the standard silicon processing methods and allows integrated circuits to be manufactured which are suitable for high frequency applications. A silicon substrate is made by sputtering a metal such as Co in a silicon wafer and then silicidizing the sputtered Co atoms by means of an annealing treatment. A top silicon wafer having a silicon dioxide layer at its bottom surface is then bonded to the sputtered layer.

Abstract: An electrical device having a voltage dependent capacitance is provided comprising a first region of a semiconductor material, and a second region and a third region of a semiconductor material formed in the first region, the second and third regions being separated by a separation region, and an electrically insulating layer formed on the first region at least at a region corresponding to the separation region, and a substantially conductive element formed on the insulating layer at least at a region corresponding to the separation region such that the insulating layer electrically insulates the substantially conductive element from the first, second and third regions, and a first electrode connected to the substantially conductive element, and a second electrode and third electrode are connected to the second and third regions. A method of manufacturing the device is also disclosed.

Abstract: In a bipolar silicon-on-insulator transistor having a substrate having a major surface, an oxide layer on the major surface, a silicon layer of a first conductivity type on the oxide layer, a base region of a second conductivity type extending into the silicon layer, an emitter region of the first conductivity type extending into the base region, and a collector region of the first conductivity type extending into the silicon layer at a lateral distance from the base region, a plug region of the second conductivity type extends into the silicon layer up to the oxide layer on the opposite side of said emitter region relative to the collector region, a portion of the plug region extends laterally along the surface of the oxide layer under at least part of the emitter region towards the collector region at a distance from the base region, and the plug region is electrically connected to the base region.

Abstract: A semiconductor device has a linear current-to-voltage characteristic through the origin of coordinates and additionally a bi-directional structure. The typical device contains an oxide layer on top of a p.sup.- doped substrate. On top of this oxide layer a n-type drift region is created which forms a longitudinal n-drift region. The n-drift region comprises at each end a low doped p-type well which has a portion with strongly doped p.sup.+ semiconductor material which will constitute contacting to either a source or a drain electrode. Each p-type well additionally contains a n.sup.+ area and additionally on top of said p-type well a gate electrode, whereby the n.sup.+ doped area is positioned in the p-well between a gate and a drain electrode or a gate and a source electrode, respectively. Thus a bi-directional double DMOS structure is created having a common drift region.

Abstract: A semiconductor device is supported by a semiconductor body which comprises a substrate, an oxide layer and a weakly doped monocrystalline wafer. Trenches for a dielectrically isolating layer which surrounds a component region are etched in the wafer. A field effect transistor in the component region has two doped wafer-line gate regions, which have been diffused in the component region with the aid of a first mask. Two heavily doped regions are diffused in the component region with the aid of a second mask, these regions forming the source region and the drain region of the transistor. The semiconductor body is easy to produce and is available commercially, which simplifies manufacture of the field effect transistor. Manufacture is also simplified because the configuration of both the component region and the parts of the transistor are determined by the simple choice of masks. The component region is weakly doped and is easy to deplete of charge carriers.

Abstract: A silicon substrate carries an isolating silicon dioxide layer and a relatively weakly and negatively doped monocrystalline silicon wafer. A component region is delimited in the wafer by an isolating layer. A bipolar transistor in the component region has a positively doped base region which includes a heavily and positively doped base connection and a heavily and negatively doped emitter. The transistor has a PN-junction at the underside of the base region and is series connected with a field effect transistor having a heavily and negatively doped drain connection. The component region is weakly doped and the distance from the PN-junction to the silicon dioxide layer is small so that a region will be readily depleted of charge carriers when applying voltages to the transistors. The voltages produce an electric field of low electrical field strength in the depleted region. This counteracts the breakthrough of a current between the base and the drain connection.

Abstract: A semiconductor device is supported by a semiconductor body which comprises a substrate, an oxide layer and a weakly doped monocrystalline wafer. Trenches for a dielectrically isolating layer which surrounds a component region are etched in the wafer. A field effect transistor in the component region has two doped wafer-line gate regions, which have been diffused in the component region with the aid of a first mask. Two heavily doped regions are diffused in the component region with the aid of a second mask, these regions forming the source region and the drain region of the transistor. The semiconductor body is easy to produce and is available commercially, which simplifies manufacture of the field effect transistor. Manufacture is also simplified because the configuration of both the component region and the parts of the transistor are determined by the simple choice of masks. The component region is weakly doped and is easy to deplete of charge carriers.