Patents by Inventor Andrew D. Henroid
Andrew D. Henroid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9727345Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.Type: GrantFiled: March 29, 2013Date of Patent: August 8, 2017Assignee: Intel CorporationInventors: Eliezer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V. Choubal, Scott D. Hahn, David A. Koufaty, Russell J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
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Publication number: 20170003724Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.Type: ApplicationFiled: September 12, 2016Publication date: January 5, 2017Inventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann
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Patent number: 9494998Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, at least one graphics engine to independently execute graphics instructions, and a power controller including an alignment logic to cause at least one workload to be executed on a first core to be rescheduled to a different time to enable the plurality of cores to be active during an active time window and to be in a low power state during an idle time window. Other embodiments are described and claimed.Type: GrantFiled: December 17, 2013Date of Patent: November 15, 2016Assignee: Intel CorporationInventors: Inder M. Sodhi, Barnes Cooper, Paul S. Diefenbaugh, Faraz A. Siddiqi, Michael Calyer, Andrew D. Henroid, Ruchika Singh
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Patent number: 9454379Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.Type: GrantFiled: December 30, 2011Date of Patent: September 27, 2016Assignee: Intel CorporationInventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann
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Patent number: 9448829Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.Type: GrantFiled: December 28, 2012Date of Patent: September 20, 2016Assignee: INTEL CORPORATIONInventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Gaurav Khanna, Russell J. Fenger, Bryant E. Bigbee, Andrew D. Henroid, David A. Koufaty
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Patent number: 9442739Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.Type: GrantFiled: December 30, 2011Date of Patent: September 13, 2016Assignee: Intel CorporationInventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann
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Publication number: 20160252943Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.Type: ApplicationFiled: February 27, 2015Publication date: September 1, 2016Inventors: Ankush Varma, Krishnakanth V. Sistla, Guy G. Sotomayor, Andrew D. Henroid, Robert E. Gough, Tod F. Schiff
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Publication number: 20160252942Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.Type: ApplicationFiled: February 27, 2015Publication date: September 1, 2016Inventors: Ankush Varma, Vasudevan Srinivasan, Eugene Gorbatov, Andrew D. Henroid, Barnes Cooper, David W. Browning, Guy M. Therien, Neil W. Songer, Krishnakanth V. Sistla, James G. Hermerding, II
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Publication number: 20160239068Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power control logic to receive power capability information from a plurality of devices to couple to the processor and allocate a platform power budget to the devices, set a first power level for the devices at which the corresponding device is allocated to be powered, communicate the first power level to the devices, and dynamically reduce a first power to be allocated to a first device and increase a second power to be allocated to a second device responsive to a request from the second device for a higher power level. Other embodiments are described and claimed.Type: ApplicationFiled: February 17, 2015Publication date: August 18, 2016Inventors: ANKUSH VARMA, KRISHNAKANTH V. SISTLA, VASUDEVAN SRINIVASAN, EUGENE GORBATOV, ANDREW D. HENROID, BARNES COOPER, DAVID W. BROWNING, GUY M. THERIEN, NEIL W. SONGER, JAMES G. HERMERDING, II
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Patent number: 9195285Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for detecting active and semi-active workloads during execution on a platform processing device and enabling a duty cycle process to reduce thermal output and power consumption, and align unaligned activity. In various embodiments, the duty cycle processing may be enabled during an active workload when thermal output or power consumption is above a thermal threshold or power consumption threshold that is below an efficient operating point for the platform processing device. The duty cycle processing may also be enabled during semi-active workloads when the workload causes the platform processing device to be underutilized and unaligned. The duty cycle processing may comprise enabling a forced idle period for the platform processing device. Other embodiments are described and claimed.Type: GrantFiled: December 27, 2012Date of Patent: November 24, 2015Assignee: INTEL CORPORATIONInventors: Eugene Gorbatov, Paul S. Diefenbaugh, Andrew D. Henroid, Guy M. Therien
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Patent number: 9110735Abstract: Methods and systems may provide for identifying a workload associated with a platform and determining a scalability of the workload. Additionally, a performance policy of the platform may be managed based at least in part on the scalability of the workload. In one example, determining the scalability includes determining a ratio of productive cycles to actual cycles.Type: GrantFiled: December 27, 2012Date of Patent: August 18, 2015Assignee: Intel CorporationInventors: Paul S. Diefenbaugh, Andrew D. Henroid, Eliezer Weissmann, Krishnakanth V. Sistla
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Publication number: 20150169036Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, at least one graphics engine to independently execute graphics instructions, and a power controller including an alignment logic to cause at least one workload to be executed on a first core to be rescheduled to a different time to enable the plurality of cores to be active during an active time window and to be in a low power state during an idle time window. Other embodiments are described and claimed.Type: ApplicationFiled: December 17, 2013Publication date: June 18, 2015Inventors: Inder M. Sodhi, Barnes Cooper, Paul S. Diefenbaugh, Faraz A. Siddiqi, Michael Calyer, Andrew D. Henroid, Ruchika Singh
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Patent number: 9026816Abstract: A method and system for determining an energy-efficient operating point of the platform or system. The platform has logic to dynamically manage setting(s) of the processing cores and/or platform components in the platform to achieve maximum system energy efficiency. By using the characteristics of the workload and/or platform to determine the optimum settings of the platform, the logic of the platform facilitates performance guarantees of the platform while minimizing the energy consumption of the processor core and/or platform. The logic of the platform identifies opportunities to run the processing cores at higher performance levels which decreases the execution time of the workload and transitions the platform to a low-power system idle state after the completion of the execution of the workload. Since the execution time of the workload is reduced, the platform spends more time in the low-power system idle state and therefore the overall system energy consumption is reduced.Type: GrantFiled: February 29, 2012Date of Patent: May 5, 2015Assignee: Intel CorporationInventors: Andrew D. Henroid, Eugene Gorbatov, Paul S. Diefenbaugh
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Patent number: 9026817Abstract: Systems and methods may provide for identifying a workload cycle for a computing platform, wherein the workload cycle is to include a busy duration and an idle duration. Additionally, platform energy consumption information may be determined for the workload cycle, and a frequency setting may be selected for the busy duration based at least in part on the platform energy consumption information.Type: GrantFiled: June 29, 2012Date of Patent: May 5, 2015Assignee: Intel CorporationInventors: Alexander W. Min, Ren Wang, Jr-Shian Tsai, Mesut A. Ergin, Tsung-Yuan C. Tai, Andrew D. Henroid, Ashish V. Choubal, Bruce L. Fleming
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Publication number: 20140281457Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.Type: ApplicationFiled: March 29, 2013Publication date: September 18, 2014Inventors: Elierzer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V. Choubal, Scott D. Hahn, David A. Koufaty, Russel J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
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Publication number: 20140189398Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for detecting active and semi-active workloads during execution on a platform processing device and enabling a duty cycle process to reduce thermal output and power consumption, and align unaligned activity. In various embodiments, the duty cycle processing may be enabled during an active workload when thermal output or power consumption is above a thermal threshold or power consumption threshold that is below an efficient operating point for the platform processing device. The duty cycle processing may also be enabled during semi-active workloads when the workload causes the platform processing device to be underutilized and unaligned. The duty cycle processing may comprise enabling a forced idle period for the platform processing device. Other embodiments are described and claimed.Type: ApplicationFiled: December 27, 2012Publication date: July 3, 2014Inventors: EUGENE GORBATOV, PAUL S. DIEFENBAUGH, ANDREW D. HENROID, GUY M. THERIEN
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Publication number: 20140189297Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, David A. Koufaty, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Gaurav Khanna, Russell J. Fenger, Bryant E. Bigbee, Andrew D. Henroid
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Publication number: 20140189694Abstract: Methods and systems may provide for identifying a workload associated with a platform and determining a scalability of the workload. Additionally, a performance policy of the platform may be managed based at least in part on the scalability of the workload. In one example, determining the scalability includes determining a ratio of productive cycles to actual cycles.Type: ApplicationFiled: December 27, 2012Publication date: July 3, 2014Inventors: Paul S. Diefenbaugh, Andrew D. Henroid, Eliezer Weissmann, Krishnakanth V. Sistla
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Publication number: 20140189301Abstract: A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload from the at least one lower processing capability compute element to the at least one higher processing capability compute element, and to determine whether or not to allow the migration based on the evaluated performance benefit. Available energy and thermal budget evaluation logic is to evaluate available energy and thermal budgets and to determine to allow the migration if the migration fits within the available energy and thermal budgets. Workload migration logic is to perform the migration when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Eugene Gorbatov, Alon Naveh, Inder M. Sodhi, Ganapati N. Srinivasa, Eliezer Weissmann, Guarav Khanna, Mishali Naik, Russell J. Fenger, Andrew D. Henroid, Dheeraj R. Subbareddy, David A. Koufaty, Paolo Narvaez
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Publication number: 20140181830Abstract: According to one embodiment, a processor includes a plurality of processor cores for executing a plurality of threads, a shared storage communicatively coupled to the plurality of processor cores, a power control unit (PCU) communicatively coupled to the plurality of processors to determine, without any software (SW) intervention, if a thread being performed by a first processor core should be migrated to a second processor core, and a migration unit, in response to receiving an instruction from the PCU to migrate the thread, to store at least a portion of architectural state of the first processor core in the shared storage and to migrate the thread to the second processor core, without any SW intervention, such that the second processor core can continue executing the thread based on the architectural state from the shared storage without knowledge of the SW.Type: ApplicationFiled: December 26, 2012Publication date: June 26, 2014Inventors: Mishali Naik, Ganapati N. Srinivasa, Alon Naveh, Inder M. Sodhi, Paolo Narvaez, Eugene Gorbatov, Eliezer Weissmann, Andrew D. Henroid, Andrew J. Herdrich, Guarav Khanna, Scott D. Hahn, Paul Brett, David A. Koufaty, Dheeraj R. Subbareddy, Abirami Prabhakaran