Patents by Inventor Andrew David Tune
Andrew David Tune has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190363829Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.Type: ApplicationFiled: May 25, 2018Publication date: November 28, 2019Inventors: Andrew David TUNE, Guanghui GENG, Zheng XU
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Publication number: 20190361486Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.Type: ApplicationFiled: May 25, 2018Publication date: November 28, 2019Inventors: Saira Samar MALIK, David Joseph HAWKINS, Andrew David TUNE, Guanghui GENG, Julian Jose Hilgemberg PONTES
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Publication number: 20190361770Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.Type: ApplicationFiled: May 25, 2018Publication date: November 28, 2019Inventors: Guanghui Geng, Andrew David Tune
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Patent number: 10489323Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.Type: GrantFiled: December 20, 2016Date of Patent: November 26, 2019Assignee: ARM LimitedInventors: Guanghui Geng, Andrew David Tune, Daniel Adam Sara, Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal
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Publication number: 20190266010Abstract: A transaction handling device comprises transaction handling circuitry to handle a transaction request for a data processing transaction, the transaction request having an associated identifier such that at least an aspect of processing for each of a set of transaction requests having the same identifier must be performed in the order of issue of that set of transactions; and detection circuitry to detect the state of an indicator associated with the identifier to indicate whether that identifier relates to more than one concurrently pending transaction request.Type: ApplicationFiled: December 13, 2017Publication date: August 29, 2019Inventors: Andrew David TUNE, Daniel SARA, Guanghui GENG
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Publication number: 20190243785Abstract: Arbitrating circuitry arbitrates between a plurality of inputs and a selection of at least one of said plurality of inputs. The arbitrating circuitry includes an array of interconnected arbiter devices operating with respect to a set of Q inputs. The array comprises M sub-levels with at least a first sub-level having T arbiter devices each operating with respect to U inputs, where Q=UM and Q=TU. For each sub-level other than a first sub-level, each arbiter device in a sub-level receives as input requests signals indicating an arbitration outcome for two or more arbiter devices in a preceding sub-level and arbitrates between those input requests.Type: ApplicationFiled: April 17, 2019Publication date: August 8, 2019Inventors: Andrew David TUNE, Peter Andrew RIOCREUX, Alessandro GRANDE
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Patent number: 10303624Abstract: Arbitrating and multiplexing circuitry for performing an arbitration between a plurality of inputs and a selection of at least one of said plurality of inputs to provide an output comprises arbitrating tree circuitry having X arbitrating levels, where X is an integer greater than one; and multiplexing tree circuitry having Y multiplexing levels, where Y is an integer greater than one; wherein (i) said Y multiplexing levels comprise a first set of said multiplexing levels upstream of a second set of said multiplexing levels; (ii) said first set of said multiplexing levels is configured to operate in parallel with at least some of said X arbitrating levels, whereby said first set of multiplexing levels is configured to perform a partial selection in parallel with said arbitration performed by said X arbitrating levels; and (iii) said second set of said multiplexing levels is configured to operate in series with said X arbitrating levels, whereby said second set of multiplexing levels completes said selection toType: GrantFiled: September 23, 2016Date of Patent: May 28, 2019Assignee: ARM LimitedInventors: Andrew David Tune, Peter Andrew Riocreux, Alessandro Grande
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Patent number: 10289587Abstract: A crossbar switch comprises two or more data inputs 10, two or more data outputs 100, a buffer 30 between the inputs and the outputs, an arbiter 52 associated with each output and configured to select data from one of the inputs when there is contention at the output, a bypass 32 associated with the buffer so that the buffer can be enabled or disabled, and a buffer controller 60 configured to enable or disable the buffer. The buffer controller further includes an accumulator 70 configured to assess whether a time-based average of the contention rate, or an average injection rate, at the output associated with the buffer, has reached a predetermined threshold. This prevents the buffer being enabled when the contention is only intermittent, which reduces power consumption without significant loss of performance.Type: GrantFiled: April 27, 2016Date of Patent: May 14, 2019Assignee: Arm LimitedInventors: Ian David Andrews, Andrew David Tune, Daniel Adam Sara, George Robert Scott Lloyd
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Patent number: 10185667Abstract: There is described a storage controller, the storage controller having an array of entries, each entry associated with a partition of one or more partitions, wherein the controller comprises logic configured to identify a partition identifier of an entry and apply a policy to the entry based on or in response to the partition identifier.Type: GrantFiled: May 25, 2017Date of Patent: January 22, 2019Assignee: Arm LimitedInventor: Andrew David Tune
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Patent number: 10169236Abstract: A cache coherency controller comprises a directory indicating, for memory addresses cached by one or more of a group of one or more cache memories connectable in a coherent cache structure, which of the cache memories are caching those memory addresses; and control circuitry configured to detect a directory entry relating to a memory address to be accessed so as to coordinate, amongst the cache memories, an access to a memory address by one of the cache memories or a coherent agent in instances when the directory entry indicates that another of the cache memories is caching that memory address; the control circuitry being responsive to status data indicating whether each cache memory in the group is currently subject to cache coherency control so as to take into account, in the detection of the directory entry relating to the memory address to be accessed, only those cache memories in the group which are currently subject to cache coherency control.Type: GrantFiled: April 20, 2016Date of Patent: January 1, 2019Assignee: ARM LimitedInventors: Sean James Salisbury, Andrew David Tune
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Publication number: 20180189097Abstract: Data processing apparatus comprises one or more transaction issuing devices configured to issue data processing transactions to be handled by a downstream device and to receive a completion acknowledgement in respect of each completed transaction; each transaction issuing device having associated transaction regulator circuitry configured to allow that transaction issuing device to issue transactions subject to a limit on a maximum number of outstanding transactions, an outstanding transaction being a transaction which has been issued but for which a completion acknowledgement has not yet been received; in which the downstream device is configured to issue an indication to a transaction issuing device, to authorise a change by the transaction regulator circuitry of the limit applicable to outstanding transactions by that transaction issuing device.Type: ApplicationFiled: January 3, 2017Publication date: July 5, 2018Inventors: Alistair Crone BRUCE, Andrew David TUNE
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Publication number: 20180173660Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.Type: ApplicationFiled: December 20, 2016Publication date: June 21, 2018Inventors: Guanghui GENG, Andrew David TUNE, Daniel Adam SARA, Phanindra Kumar MANNAVA, Bruce James MATHEWSON, Jamshed JALAL
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Patent number: 9977742Abstract: A cache coherency controller comprises a directory indicating, for memory addresses cached by a group of two or more cache memories in a coherent cache structure, which of the cache memories are caching those memory addresses, the directory being associative so that multiple memory addresses map to an associative set of more than one directory entry; and control logic responsive to a memory address to be newly cached, and configured to detect whether one or more of the set of directory entries mapped to that memory address is available for storage of an indication of which of the two or more cache memories are caching that memory address; the control logic being configured so that when all of the set of directory entries mapped to that memory address are occupied, the control logic is configured to select one of the set of directory entries as a directory entry to be overwritten and the corresponding cached information to be invalidated, the control logic being configured to select a directory entry to be oveType: GrantFiled: April 20, 2016Date of Patent: May 22, 2018Assignee: ARM LimitedInventors: Andrew David Tune, Sean James Salisbury
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Patent number: 9928195Abstract: An interconnect, and method of operation of an interconnect, are provided for connecting a plurality of master devices and a plurality of slave devices. Hazard management circuitry is used to serialize transactions to overlapping addresses. In addition, gating circuitry ensures ordered write observation (OWO) behavior at an interface to one or more of the master devices, the gating circuitry receiving write address transfers of write transactions and performing a gating operation to gate onward propagation of the write address transfers to the slave devices in order to ensure the OWO behavior. The gating circuitry performs the gating operation under control of the hazard management circuitry. Hence, for write transactions that are subjected to hazard checking by the hazard management circuitry, this removes the need to implement any other processes to specifically manage OWO behavior for those write transactions.Type: GrantFiled: December 4, 2015Date of Patent: March 27, 2018Assignee: ARM LimitedInventors: Andrew David Tune, Peter Andrew Riocreux, Sean James Salisbury, Daniel Adam Sara, George Robert Scott Lloyd
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Patent number: 9906440Abstract: Arbitrating and multiplexing circuitry 28 comprises arbitrating tree circuitry having X arbitrating levels and multiplexing tree circuitry having Y multiplexing levels. The Y multiplexing levels comprise a first set of multiplexing levels upstream of a second set of multiplexing levels. The first set of multiplexing levels operate in parallel with at least some of the arbitrating levels. The second set of multiplexing levels operate in series with the X arbitrating levels such that the second set of multiplexing levels completes the required selection to provide the final output following completion of, and in dependence upon, the arbitration by the arbitrating tree circuitry.Type: GrantFiled: June 9, 2015Date of Patent: February 27, 2018Assignee: ARM LimitedInventors: Rakesh Raman, Andrew David Tune, Guanghui Geng
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Patent number: 9892072Abstract: Interconnect circuitry for connecting transaction masters to transaction slaves includes response modification circuitry. The response modification circuitry includes shortlist buffer circuitry storing identification for modification target transaction responses. The response modification circuitry uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master.Type: GrantFiled: October 5, 2015Date of Patent: February 13, 2018Assignee: ARM LimitedInventors: Andrew David Tune, Arthur Brian Laughton, Daniel Adam Sara, Sean James Salisbury, Peter Andrew Riocreux
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Patent number: 9852088Abstract: A system-on-check integrated circuit 2 includes interconnect circuitry 4 connecting a plurality of transaction sources to a plurality of transaction destinations. The interconnect circuitry 4 includes a reorder buffer for buffering access transactions and hazard checking circuitry 46, 48, 50, 52 for performing hazard checks, such as point-of-serialization checks and identifier reuse checks. Check suppression circuitry 62, 64, 66, 68 serves to suppress one or more hazard checks depending upon one or more state variables that themselves depend upon access transactions other than the access transaction for which the hazard checking is or is not to be suppressed. As an example, hazard checking may be suppressed if it is known that there are no other access transactions currently buffered within the reorder buffer 26 or alternatively no other access transactions from the same transaction source buffered within the reorder buffer 26.Type: GrantFiled: February 23, 2015Date of Patent: December 26, 2017Assignee: ARM LimitedInventors: Andrew David Tune, Daniel Sara, Sean James Salisbury, Arthur Laughton, Peter Andrew Riocreux
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Publication number: 20170357597Abstract: There is described a storage controller, the storage controller having an array of entries, each entry associated with a partition of one or more partitions, wherein the controller comprises logic configured to identify a partition identifier of an entry and apply a policy to the entry based on or in response to the partition identifier.Type: ApplicationFiled: May 25, 2017Publication date: December 14, 2017Applicant: ARM LTDInventor: Andrew David TUNE
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Publication number: 20170315947Abstract: A crossbar switch comprises two or more data inputs 10, two or more data outputs 100, a buffer 30 between the inputs and the outputs, an arbiter 52 associated with each output and configured to select data from one of the inputs when there is contention at the output, a bypass 32 associated with the buffer so that the buffer can be enabled or disabled, and a buffer controller 60 configured to enable or disable the buffer. The buffer controller further includes an accumulator 70 configured to assess whether a time-based average of the contention rate, or an average injection rate, at the output associated with the buffer, has reached a predetermined threshold. This prevents the buffer being enabled when the contention is only intermittent, which reduces power consumption without significant loss of performance.Type: ApplicationFiled: April 27, 2016Publication date: November 2, 2017Applicant: ARM LimitedInventors: Ian David ANDREWS, Andrew David TUNE, Daniel Adam SARA, George Robert Scott LLOYD
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Patent number: 9727466Abstract: An interconnect and method of managing a snoop filter within such an interconnect are provided. The interconnect is used to connect a plurality of devices, including a plurality of master devices where one or more of the master devices has an associated cache storage. The interconnect comprises coherency control circuitry to perform coherency control operations for data access transactions received by the interconnect from the master devices. In performing those operations, the coherency control circuitry has access to snoop filter circuitry that maintains address-dependent caching indication data, and is responsive to a data access transaction specifying a target address to produce snoop control data providing an indication of which master devices have cached data for the target address in their associated cache storage.Type: GrantFiled: August 11, 2015Date of Patent: August 8, 2017Assignee: ARM LimitedInventors: Andrew David Tune, Sean James Salisbury