Abstract: Arbitration circuitry for arbitrating between a plurality W of requests R for access to a shared resource. Included are state bits storage storing I state bits Q and generating 2I output bits comprising the true and compliment values of each stored state bit and routing circuitry for generating a set of mask signals M from the output bits. Grant circuitry receives the set of mask signals and the plurality of requests, and grants access to the shared resource to an asserted request having regard to the priority ordering encoded by the set of mask signals. State bit update circuitry is responsive to a trigger condition to perform an update causing a change in the priority ordering encoded by the set of mask signals. The routing circuitry provides a pattern of connections such that each mask signal in the set is directly connected to one of said output bits.

Abstract: An integrated circuit includes one or more transaction data sources and one or more transaction data destinations connected via interconnect circuitry comprising a plurality of interconnect nodes. Within the interconnect nodes there are one or more converging interconnect nodes. A converging interconnect node includes prediction data generation circuitry for reading characteristics of a current item of transaction data from the converging interconnect node and generating associated prediction data for a future item of transaction data which will be returned to the converging interconnect node at a predetermined time in the future. This prediction data is stored within prediction data storage circuitry and is read by prediction data evaluation circuitry to control processing of a future item of transaction data corresponding to that prediction data when it is returned to the converging interconnect node. The interconnect circuitry may have a branching network topology or recirculating ring based topology.

Abstract: Transaction requests requesting a service from the slave device are received from a master device at a transaction interface. The transaction requests are selectively issued to the bus system under control of an issue control circuit. A target outstanding transaction value N.x is received at a control interface. The target outstanding transaction value has an integer portion N and a fractional portion x. The issue control circuit controls the transaction interface to issue the transaction requests to the bus system in dependence upon the target outstanding transaction value so that a time averaged number of outstanding transaction requests corresponds to the target outstanding transaction value.

Abstract: A communication infrastructure for a data processing apparatus, and a method of operation of such a communication infrastructure are provided. The communication infrastructure provides first and second switching circuits interconnected via a bidirectional link. Both of the switching circuits employ a multi-channel communication protocol, such that for each transaction a communication path is established from an initiating master interface to a target slave interface, with that communication path comprising m channels. The m channels comprise one or more forward channels from the initiating master interface to the target slave interface and one or more reverse channels from the target slave interface to the initiating master interface, and handshaking signals are associated with each of the m channels.

Abstract: An integrated circuit includes a signal source and a signal destination linked by a signal path. Error correction codes (e.g. Hamming codes) are applied to the signals to be transmitted. Errors detected in the signal transmission are used to control an operating parameter of the signal path, such as signal voltage level, body bias voltage, clock frequency and/or temperature. The control applied is closed-loop feedback control seeking to maintain a finite non-zero predetermined error rate. The technique can also be used between a memory accessing integrated circuit and a separate memory integrated circuit. Furthermore, the technique can be used to provide fixed, but differing operating parameters for signal lines within a signal path.

Abstract: A bus interconnect device is provided comprising a parallel plate waveguide for coupling together a plurality of devices. This provides an efficient and flexible approach for providing interconnect functionality within a data processing apparatus.

Abstract: Transaction requests requesting a service from the slave device are received from a master device at a transaction interface. The transaction requests are selectively issued to the bus system under control of an issue control circuit. A target outstanding transaction value N.x is received at a control interface. The target outstanding transaction value has an integer portion N and a fractional portion x. The issue control circuit controls the transaction interface to issue the transaction requests to the bus system in dependence upon the target outstanding transaction value so that a time averaged number of outstanding transaction requests corresponds to the target outstanding transaction value.

Abstract: A data processing apparatus has initiator circuitry for initiating a transfer of payload data in a first clock cycle, and recipient circuitry for receiving the payload data in a later clock cycle. A communication channel carries the payload data along with associated transfer control information. Timing of receipt of the payload data by the recipient circuitry is controlled by the transfer control information. Timing easing circuitry located within the communication channel temporarily buffers the transfer control information before outputting it to the recipient circuitry. The timing easing circuitry is responsive to a specified timing easing value to determine a time for which the transfer control information is temporarily buffered. The number of clock cycles that elapses between the first clock cycle and the later clock cycle depends on the specified timing easing value. This enables a multi-cycle path to be provided to transfer the payload data.

Abstract: A communication infrastructure for a data processing apparatus, and a method of operation of such a communication infrastructure are provided. The communication infrastructure provides first and second switching circuits interconnected via a bidirectional link. Both of the switching circuits employ a multi-channel communication protocol, such that for each transaction a communication path is established from an initiating master interface to a target slave interface, with that communication path comprising m channels. The m channels comprise one or more forward channels from the initiating master interface to the target slave interface and one or more reverse channels from the target slave interface to the initiating master interface, and handshaking signals are associated with each of the m channels.

Abstract: A data processing apparatus includes a first component for generating a signal operating in the first clock domain having a first clock period, and a second component for receiving the signal operating in the second clock domain having a second clock period. The second clock period is synchronous with but slower than the first clock period. Interface circuitry is provided for translating the signal between the first clock domain and the second clock domain, the interface circuitry operating in the first clock domain and comprising a storage element for temporarily buffering the signal generated by the first component before outputting that signal to the second component. Enable circuitry is used to control output of the signal from the storage element having regard to a specified input delay value identifying an input delay time of the second component expressed in terms of the first clock period.

Abstract: A data processing apparatus and method are providing for arbitrating access to a shared resource. The data processing apparatus has a plurality of logic elements sharing access to the shared resource, and arbitration circuitry which is responsive to requests by one or more of the logic elements for access to the shared resource to perform a priority determination operation to select one of the requests as a winning request. The arbitration circuitry applies an arbitration policy to associate priorities with each logic element, the arbitration policy comprising multiple priority groups, each priority group having a different priority and containing at least one of the logic elements. Within each priority group, the arbitration circuitry applies a priority ordering operation to attribute relative priorities to the logic elements within that priority group.

Abstract: An integrated circuit (2) includes a signal source (4, 6) and a signal destination (10, 12) linked by a signal path (8). Error correction codes (e.g. Hamming codes) are applied to the signals to be transmitted. Errors detected in the signal transmission are used to control an operating parameter of the signal path, such as signal voltage level, body bias voltage, clock frequency and/or temperature. The control applied is closed-loop feedback control seeking to maintain a finite non-zero predetermined error rate. The technique can also be used between a memory accessing integrated circuit (54) and a separate memory integrated circuit (56). Furthermore, the technique can be used to provide fixed, but differing operating parameters for signal lines within a signal path.

Abstract: A bus interconnect device is provided comprising a parallel plate waveguide for coupling together a plurality of devices. This provides an efficient and flexible approach for providing interconnect functionality within a data processing apparatus.

Abstract: A data processing apparatus and method are provided for controlling a transfer of payload data over a communication channel. The data processing apparatus has initiator circuitry for initiating a transfer of payload data in a first clock cycle, and recipient circuitry for receiving the payload data the subject of the transfer in a later clock cycle. A communication channel is provided over which the payload data is passed from the initiator circuitry to the recipient circuitry along with associated transfer control information, timing of receipt of the payload data by the recipient circuitry being controlled by the transfer control information. Timing easing circuitry located within the communication channel is then used to temporarily buffer at least the transfer control information generated by the initiator circuitry before outputting that transfer control information to the recipient circuitry.

Abstract: The present invention provides a data processing apparatus and method for translating a signal between a first clock domain and a second clock domain. The data processing apparatus may comprise a first component for generating a signal, the first component operating in the first clock domain having a first clock period, and a second component for receiving the signal, the second component operating in the second clock domain having a second clock period. In one embodiment, the second clock period is synchronous with but slower than the first clock period. Interface circuitry is provided for translating the signal between the first clock domain and the second clock domain, the interface circuitry operating in the first clock domain and comprising a storage element for temporarily buffering the signal generated by the first component before outputting that signal to the second component.

Abstract: A data processing apparatus and method are providing for arbitrating access to a shared resource. The data processing apparatus has a plurality of logic elements sharing access to the shared resource, and arbitration circuitry which is responsive to requests by one or more of the logic elements for access to the shared resource to perform a priority determination operation to select one of the requests as a winning request. The arbitration circuitry applies an arbitration policy to associate priorities with each logic element, the arbitration policy comprising multiple priority groups, each priority group having a different priority and containing at least one of the logic elements. Within each priority group, the arbitration circuitry applies a priority ordering operation to attribute relative priorities to the logic elements within that priority group.

Abstract: An interconnect block for a data processing apparatus, said interconnect block being operable to provide data routes via which one or more initiator devices may access one or more recipient devices, said interconnect block comprising: a first and a second portion; said first portion comprising at least one initiator port for communicating with one of said initiator devices, and at least one recipient port for communicating with one of said recipient devices; said second portion comprising at least two recipient ports for communicating with at least two recipient devices, said second portion being connected to said first portion via at least two parallel connecting routes, said at least two recipient ports being connectable to said at least two parallel connecting routes; wherein in response to a request received from one of said initiator devices at said first portion to perform a transaction accessing one of said at least two recipients in communication with said second portion, said interconnect block is op

Abstract: A data processing apparatus and method are provided for controlling access to a slave device, the slave device having an address range associated therewith. The apparatus comprises control storage programmable to define a partition identifying a secure region and a non-secure region in the address range, with the data processing apparatus supporting a plurality of modes of operation including a secure mode, and the control storage being programmable only by software executing in the secure mode. A master device is arranged to issue an access request onto a bus, the access request identifying a sequence of addresses within the address range and including a control signal indicating whether the access request is a secure access request or a non-secure access request. The secure region is only accessible by a secure access request.