Patents by Inventor Andrew E. Phelps

Andrew E. Phelps has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8028130
    Abstract: A method and apparatus for implementation of a pipeline structure for data transfer. A request is received from a first domain to access a second domain during a first clock cycle. A pipeline structure is used to perform at least a portion of the request during a subsequent clock cycle.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: September 27, 2011
    Assignee: Oracle America, Inc.
    Inventors: Steven F. Weiss, Andrew E. Phelps, Patricia Shanahan
  • Patent number: 7251748
    Abstract: A method of utilizing timestamps for the global ordering of event information, particularly hardware error reporting, is disclosed. Locally generated time stamps are associated with hardware errors or other events. The timestamps form the basis for the global ordering of event information. The timestamps are normalized, either through a pre-synchronization process with a common time, or through the use of offsets maintained either locally near system chips or by the system processor. Once normalized, the timestamps can be compared to determine a first occurring event among multiple reported events.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: July 31, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Dean A. Liberty, Andrew E. Phelps, David L. Isaman
  • Patent number: 7055016
    Abstract: A computer system including a memory controller configured to perform pre-fetch operations. A computer system includes a first system memory, a second system memory and a first and a second memory controller which are coupled to the first and second system memories, respectively. Each system memory may include at least one memory module including volatile storage. The first memory controller may be configured read data from the first system memory corresponding to an address of a current memory request. Further the second memory controller may be configured to selectively pre-fetch data from the second system memory depending upon selected address bits of the address of the current memory request.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: May 30, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Andrew E. Phelps, Anders Landin, Jurgen Schulz
  • Patent number: 7020753
    Abstract: The present invention provides a method and apparatus for inter-domain data transfer. The method includes mapping a memory region of a source device into a central device and mapping a memory region of a target device into the central device. The method further includes transferring data from the mapped memory region of the source device to the mapped memory region of the target device.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: March 28, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Patricia Shanahan, Andrew E. Phelps, Guy David Frick
  • Patent number: 6961827
    Abstract: The present invention provides a method and apparatus for invalidating a victimized entry. The apparatus comprises a directory cache adapted to store one or more cache entries, and a control unit. The control unit is adapted to determine whether it is desirable to remove a shared cache entry from the directory cache, and invalidate the shared cache entry in response to determining that it is desirable to remove the shared cache entry from the directory cache.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: November 1, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Patricia Shanahan, Andrew E. Phelps, Nicholas E. Aneshansley
  • Patent number: 6920584
    Abstract: The present invention provides a method and apparatus for design verification. The method comprises operating a device in the system in a first state, modifying at least one operational characteristic of the device to operate in a second state, and determining if an error condition occurs in the system in response to modifying the operational characteristic of the device. The apparatus comprises an interface and a verification module adapted to receive a control signal from the interface and to adjust an operating characteristic of the apparatus to exercise a system in a manner that is capable of revealing one or more error conditions in the system in response to receiving the control signal.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: July 19, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Andrew E. Phelps, Steven F. Weiss
  • Patent number: 6915450
    Abstract: A method for communicating transactions includes providing an interconnect having a plurality of ports for communicating transactions between a plurality of domains in a computing system is provided. Each port is associated with a subset of the domains. The interconnect includes a first signal path for transmitting a first portion of the transaction and a second signal path for transmitting a second portion of the transaction. A transaction issued from a port associated with more than one of the domains is identified. An error in one of the first and second portions of the transaction is identified. The transaction is canceled responsive to identifying the error. A computing system for communicating transactions includes first and second devices. The first device is adapted to receive a first portion of a transaction. The second device is adapted to receive a second portion of the transaction in lockstep with respect to the first device.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: July 5, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Andrew E. Phelps, Thomas P. Van Wormer, Gary L. Riddle
  • Patent number: 6898728
    Abstract: A method and apparatus for reconfiguring a computing system on a system domain-by-system domain basis are disclosed. In one aspect of the present invention, the apparatus is a computing system comprises a plurality of system domains, a centerplane interconnecting the system domains, and a system controller. The system controller is capable of detecting a condition triggering a reconfiguration and reconfiguring a signal path affected by the condition from a first mode to a second mode.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: May 24, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Daniel P. Drogichen, Andrew E. Phelps
  • Patent number: 6877108
    Abstract: A method and apparatus for providing error isolation in a multi-domain computer system. The system includes a plurality of system resources allocated to form at least a first and second domain. The system resources of the first domain perform a set of transactions independent from a set of transactions performed by the system resources of the second domain. The system further comprises at least one interface for coupling one system resource from the first domain and one system resource from the second domain. The at least one interface tracks the set of transactions performed by the one system resource of the first domain and the one system resource of the second domain independently from one another.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: April 5, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Donald Kane, Steven Fitzgerald Weiss, Eric E. Graf, Andrew E. Phelps
  • Patent number: 6871294
    Abstract: A method and apparatus for dynamically reconfiguring a computing system are disclosed. The method comprises detecting a predetermined condition triggering a reconfiguration of the computing system; and dynamically reconfiguring a signal path affected by the condition from a first mode to a second mode responsive to detecting the condition. The apparatus is a computing system, comprising: a plurality of I/O switches, a crossbar switch, a plurality of signal paths; and a system controller. Each signal path is defined by an I/O switch and the crossbar switch. The system controller is capable of detecting a predetermined condition triggering a reconfiguration and dynamically reconfiguring at least one of the signal paths affected by the condition from a first mode to a second mode.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: March 22, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Andrew E. Phelps, Daniel P. Drogichen, Donald B. Kay
  • Publication number: 20040221111
    Abstract: A computer system including a memory controller configured to perform pre-fetch operations. A computer system includes a first system memory, a second system memory and a first and a second memory controller which are coupled to the first and second system memories, respectively. Each system memory may include at least one memory module including volatile storage. The first memory controller may be configured read data from the first system memory corresponding to an address of a current memory request. Further the second memory controller may be configured to selectively pre-fetch data from the second system memory depending upon selected address bits of the address of the current memory request.
    Type: Application
    Filed: April 30, 2003
    Publication date: November 4, 2004
    Applicant: Sun Microsystems, Inc.
    Inventors: Andrew E. Phelps, Anders Landin, Jurgen Schulz
  • Patent number: 6721852
    Abstract: The present invention provides a method and apparatus for updating a directory cache. The method comprises detecting a memory access transaction, determining a retention value based on the type of memory access transaction, and storing the retention value in an entry associated with the memory access transaction.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: April 13, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Patricia Shanahan, Andrew E. Phelps
  • Publication number: 20030131213
    Abstract: The present invention provides a method and apparatus for inter-domain data transfer. The method includes mapping a memory region of a source device into a central device and mapping a memory region of a target device into the central device. The method further includes transferring data from the mapped memory region of the source device to the mapped memory region of the target device.
    Type: Application
    Filed: January 9, 2002
    Publication date: July 10, 2003
    Inventors: Patricia Shanahan, Andrew E. Phelps, Guy David Frick
  • Patent number: 6571360
    Abstract: A multiprocessing computer system provides the hardware support to properly test an I/O board while the system is running user application programs and while preventing a faulty board from causing a system crash. The system includes a centerplane that mounts multiple expander boards. Each expander board in turn connects a microprocessor board and an I/O board to the centerplane. Prior to testing, the replacement I/O board becomes a part of a dynamic system domain software partition after it has been inserted into an expander board of the multiprocessing computer system. Testing an I/O board involves executing a process using a microprocessor and memory on a microprocessor board to perform hardware tests on the I/O board. An error cage, address transaction cage, and interrupt transaction cage isolate any errors generated while the I/O board is being tested.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: May 27, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Daniel P. Drogichen, Eric Eugene Graf, Don Kane, Douglas B. Meyer, Andrew E. Phelps, Patricia Shanahan, Steven F. Weiss
  • Publication number: 20030093722
    Abstract: The present invention provides a method and apparatus for invalidating a victimized entry. The apparatus comprises a directory cache adapted to store one or more cache entries, and a control unit. The control unit is adapted to determine whether it is desirable to remove a shared cache entry from the directory cache, and invalidate the shared cache entry in response to determining that it is desirable to remove the shared cache entry from the directory cache.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Inventors: Patricia Shanahan, Andrew E. Phelps, Nicholas E. Aneshansley
  • Publication number: 20030088808
    Abstract: The present invention provides a method and apparatus for design verification. The method comprises operating a device in the system in a first state, modifying at least one operational characteristic of the device to operate in a second state, and determining if an error condition occurs in the system in response to modifying the operational characteristic of the device. The apparatus comprises an interface and a verification module adapted to receive a control signal from the interface and to adjust an operating characteristic of the apparatus to exercise a system in a manner that is capable of revealing one or more error conditions in the system in response to receiving the control signal.
    Type: Application
    Filed: November 2, 2001
    Publication date: May 8, 2003
    Applicant: Sun Microsystems, Inc.
    Inventors: Andrew E. Phelps, Steven F. Weiss
  • Publication number: 20030084373
    Abstract: A method for communicating transactions includes providing an interconnect having a plurality of ports for communicating transactions between a plurality of domains in a computing system is provided. Each port is associated with a subset of the domains. The interconnect includes a first signal path for transmitting a first portion of the transaction and a second signal path for transmitting a second portion of the transaction. A transaction issued from a port associated with more than one of the domains is identified. An error in one of the first and second portions of the transaction is identified. The transaction is canceled responsive to identifying the error. A computing system for communicating transactions includes first and second devices. The first device is adapted to receive a first portion of a transaction. The second device is adapted to receive a second portion of the transaction in lockstep with respect to the first device.
    Type: Application
    Filed: November 1, 2001
    Publication date: May 1, 2003
    Applicant: Sun Microsystems, Inc.
    Inventors: Andrew E. Phelps, Thomas P. Van Wormer, Gary L. Riddle
  • Publication number: 20030079086
    Abstract: The present invention provides a method and apparatus for updating a directory cache. The method comprises detecting a memory access transaction, determining a retention value based on the type of memory access transaction, and storing the retention value in an entry associated with the memory access transaction.
    Type: Application
    Filed: October 17, 2001
    Publication date: April 24, 2003
    Inventors: Patricia Shanahan, Andrew E. Phelps
  • Publication number: 20030061476
    Abstract: A method and apparatus for dynamically reconfiguring a computing system are disclosed. The method comprises detecting a predetermined condition triggering a reconfiguration of the computing system; and dynamically reconfiguring a signal path affected by the condition from a first mode to a second mode responsive to detecting the condition. The apparatus is a computing system, comprising: a plurality of I/O switches, a crossbar switch, a plurality of signal paths; and a system controller. Each signal path is defined by an I/O switch and the crossbar switch. The system controller is capable of detecting a predetermined condition triggering a reconfiguration and dynamically reconfiguring at least one of the signal paths affected by the condition from a first mode to a second mode.
    Type: Application
    Filed: September 25, 2001
    Publication date: March 27, 2003
    Inventors: Andrew E. Phelps, Daniel P. Drogichen, Donald B. Kay
  • Publication number: 20030061538
    Abstract: A method and apparatus for providing error isolation in a multi-domain computer system. The system includes a plurality of system resources allocated to form at least a first and second domain. The system resources of the first domain perform a set of transactions independent from a set of transactions performed by the system resources of the second domain. The system further comprises at least one interface for coupling one system resource from the first domain and one system resource from the second domain. The at least one interface tracks the set of transactions performed by the one system resource of the first domain and the one system resource of the second domain independently from one another.
    Type: Application
    Filed: September 25, 2001
    Publication date: March 27, 2003
    Inventors: Donald Kane, Steven Fitzgerald Weiss, Eric E. Graf, Andrew E. Phelps