Abstract: A page service request is received from a peripheral device requesting that a memory page be loaded into system memory. Page service request information corresponding to the received page service request is written as a queue entry into a queue structure in system memory. The processor is notified that the page request is present in the queue. The processor may be notified with an interrupt of a new queue entry. The processor processes the page service request and the peripheral device is notified of the completion of the processing of the request.

Abstract: Embodiments allow a smaller, simpler hardware implementation of an input/output memory management unit (IOMMU) having improved translation behavior that is independent of page table structures and formats. Embodiments also provide device-independent structures and methods of implementation, allowing greater generality of software (fewer specific software versions, in turn reducing development costs).

Abstract: An input/output memory management unit (IOMMU) configured to control requests by an I/O device to a system memory includes control logic that may perform a two-level guest translation to translate an address associated with an I/O device-generated request using translation data stored in the system memory. The translation data includes a device table having a number of entries. The control logic may select the device table entry for a given request by the using a device identifier that corresponds to the I/O device that generates the request. The translation data may also include a first set of I/O page tables including a set of guest page tables and a set of nested page tables.

Abstract: An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may translate an address received in a request from the I/O device. If the request includes a transaction layer protocol (TLP) packet with a process address space identifier (PASID) prefix, the control logic may perform a two-level guest translation. Accordingly, the control logic may access a set of guest page tables to translate the address received in the request. A pointer in a last guest page table points to a first table in a set of nested page tables. The control logic may use the pointer in a last guest page table to access the set of nested page tables to obtain a system physical address (SPA) that corresponds to a physical page in the system memory. The cache memory stores completed translations.

Abstract: In one embodiment, an input/output memory management unit (IOMMU) comprises a control register and control logic coupled to the control register. The control register is configured to store a base address of a device table, wherein a given input/output (I/O) device has an associated device identifier that selects a first entry in the device table. The first entry comprises a pointer to an interrupt remapping table. The control logic is configured to remap an interrupt specified by an interrupt request received by the IOMMU from the given I/O device if the interrupt remapping table includes an entry for the interrupt.

Abstract: In one embodiment, an input/output memory management unit (IOMMU) comprises a control register configured to store a base address of a set of translation tables and control logic coupled to the control register. The control logic is configured to respond to an input/output (I/O) device-initiated request having an address within an address range of an address space corresponding to a peripheral interconnect. One or more operations other than a memory operation are associated with the address range, and the control logic is configured to translate the address to a second address outside of the address range if the translation tables specify a translation from the address to the second address, whereby a memory operation is performed in response to the request instead of the one or more operations associated with the address range.

Abstract: A solution for evaluating trust in a computer infrastructure is provided. In particular, a plurality of computing devices in the computer infrastructure evaluate one or more other computing devices in the computer infrastructure based on a set of device measurements for the other computing device(s) and a set of reference measurements. To this extent, each of the plurality of computing devices also provides a set of device measurements for processing by the other computing device(s) in the computer infrastructure.

Abstract: In an embodiment, a system memory stores a set of input/output (I/O) translation tables. One or more I/O devices initiate direct memory access (DMA) requests including virtual addresses. An I/O memory management unit (IOMMU) is coupled to the I/O devices and the system memory, wherein the IOMMU is configured to translate the virtual addresses in the DMA requests to physical addresses to access the system memory according to an I/O translation mechanism implemented by the IOMMU. The IOMMU comprises one or more caches, and is configured to read translation data from the I/O translation tables responsive to a prefetch command that specifies a first virtual address. The reads are responsive to the first virtual address and the I/O translation mechanism, and the IOMMU is configured to store data in the caches responsive to the read translation data.

Abstract: A method is disclosed for discovering servers, spawning collector threads to collect information from servers, and reporting such information. The method may determine a number of servers communicatively coupled to a network. For each server, a collector thread may be spawned to collect information regarding the server by sending requests to the server and receiving responses from the server. The collector threads may be spawned by and run on a computing device other than the number of servers, such that no computer-executable code is installed on the servers for collecting the information. Upon completion of the collector thread for each server, the information regarding the server as collected may be stored to a database by one or more writer threads.

Abstract: A solution for evaluating trust in a computer infrastructure is provided. In particular, a plurality of computing devices in the computer infrastructure evaluate one or more other computing devices in the computer infrastructure based on a set of device measurements for the other computing device(s) and a set of reference measurements. To this extent, each of the plurality of computing devices also provides a set of device measurements for processing by the other computing device(s) in the computer infrastructure.

Abstract: Server discovery, spawning collector threads to collect information from servers, and reporting such information, is disclosed. A method of one embodiment determines a number of servers communicatively coupled to a network. For each server, a collector thread is spawned to collect information regarding the server by sending requests to the server and receiving responses from the server. The collector threads can be spawned by and run on a computing device other than the number of servers, such that no computer-executable code is installed on the servers for collecting the information. Upon completion of the collector thread for each server, the information regarding the server as collected is stored to a database by one or more writer threads.

Abstract: In an embodiment, a system memory stores a set of input/output (I/O) translation tables. One or more I/O devices initiate direct memory access (DMA) requests including virtual addresses. An I/O memory management unit (IOMMU) is coupled to the I/O devices and the system memory, wherein the IOMMU is configured to translate the virtual addresses in the DMA requests to physical addresses to access the system memory according to an I/O translation mechanism implemented by the IOMMU. The IOMMU comprises one or more caches, and is configured to read translation data from the I/O translation tables responsive to a prefetch command that specifies a first virtual address. The reads are responsive to the first virtual address and the I/O translation mechanism, and the IOMMU is configured to store data in the caches responsive to the read translation data.

Abstract: Indicating when the cover for a computer chassis has been opened is disclosed. A computer of an embodiment of the invention includes a chassis and a basic input/output system (BIOS), or another type of firmware. The chassis has an openable cover, and circuitry indicating when the openable cover has been opened. The BIOS has a non-volatile memory in which a flag is set when the circuitry indicates that the openable cover has been opened. The computer may further include always-on circuitry, such as time-of-day and real-time clock circuitry, to which the circuitry indicating when the openable cover has been opened is electrically connected. The computer may also include one or more encryption and/or signing modules that encrypt and/or sign data according to one or more keys. The keys are rendered invalid when the cover of the chassis has been opened.

Abstract: In one embodiment, an input/output memory management unit (IOMMU) comprises a control register and control logic coupled to the control register. The control register is configured to store a base address of a device table, wherein a given input/output (I/O) device has an associated device identifier that selects a first entry in the device table. The first entry comprises a pointer to an interrupt remapping table. The control logic is configured to remap an interrupt specified by an interrupt request received by the IOMMU from the given I/O device if the interrupt remapping table includes an entry for the interrupt.

Abstract: In one embodiment, an input/output memory management unit (IOMMU) comprises a control register configured to store a base address of a set of translation tables and control logic coupled to the control register. The control logic is configured to respond to an input/output (I/O) device-initiated request having an address within an address range of an address space corresponding to a peripheral interconnect. One or more operations other than a memory operation are associated with the address range, and the control logic is configured to translate the address to a second address outside of the address range if the translation tables specify a translation from the address to the second address, whereby a memory operation is performed in response to the request instead of the one or more operations associated with the address range.

Abstract: A solution for evaluating trust in a computer infrastructure is provided. In particular, a plurality of computing devices in the computer infrastructure evaluate one or more other computing devices in the computer infrastructure based on a set of device measurements for the other computing device(s) and a set of reference measurements. To this extent, each of the plurality of computing devices also provides a set of device measurements for processing by the other computing device(s) in the computer infrastructure.