Abstract: A column driver for a matrix addressed display such as a liquid crystal display (LCD) is disclosed. The column driver accepts 10-bit inputs, provides 1024 distinct output levels, and is compatible with digital gamma correction by way of, for example, an EPROM lookup table. A complete column driver includes a group of chips which are serially interconnected and receive all the external signals applied in parallel. Only one chip is made active at any instant of time, in order to save power. In each IC, selective polarity inversion of the 10-bit data is carried out before feeding it to a switched capacitor digital to analog converter (CAPDAC) which operates in either a high or low voltage range. All CAPDACs are loaded simultaneously and present a precise output for approximately 95% of each linetime. Each CAPDAC output is connected to a buffer opamp via two CMOS switches which cause the CAPDAC to simultaneously yet transparently change range and allow the opamp buffer to continue driving.

Abstract: Disclosed is a technique for driving a column of pixels implemented using O-LEDs. The technique includes separate, digitally adjustable current sources on each column conductor of the array. For each column, the digitally-programmed current flow terminates with a reference O-LED and a series NMOS transistor forming the input leg of a novel, distributed current mirror. The current is "mirrored" to the output leg of the distributed current mirror which can service any one of a plurality of active O-LEDs in the column based on a row select signal. In this way, a transistor on the output leg of the current mirror couples its respective O-LED to a source of operational power. The mirrored charge on the gate of the output leg transistor causes it to apply the same current to the active O-LED as was applied to the reference O-LED through the input leg transistor. Additionally, the voltage drop across the NMOS transistor and the reference O-LED is used to charge a capacitor associated with the selected O-LED.

Abstract: A column driver for a matrix addressed display such as a liquid crystal display (LCD) is disclosed. The column driver accepts 10-bit inputs, provides 1024 distinct output levels, and is compatible with digital gamma correction by way of, for example, an EPROM lookup table. A complete column driver includes a group of chips which are serially interconnected and receive all the external signals applied in parallel. Only one chip is made active at any instant of time, in order to save power. In each IC, selective polarity inversion of the 10-bit data is carried out before feeding it to a switched capacitor digital to analog converter (CAPDAC) which operates in either a high or low voltage range. All CAPDACs are loaded simultaneously and present a precise output for approximately 95% of each linetime. Each CAPDAC output is connected to a buffer opamp via two CMOS switches which cause the CAPDAC to simultaneously yet transparently change range and allow the opamp buffer to continue driving.

Abstract: In an array of a liquid crystal display device having data lines and row select lines, a pair of conductors are provided in a direction transverse to that of the row select lines at opposite sides of the display device. The conductors are capacitively coupled to the row select lines. An amplifier is responsive to a signal generated in one of the conductors from capacitively coupled disturbance signals developed in the row select lines. The amplifier develops an output signal at the other conductor that is also capacitively coupled to the row select lines in a manner that tends to reduce the disturbance signals.

Abstract: A shift register for scanning a liquid crystal display includes cascaded stages. A given stage is formed with an input transistor switch that is responsive to an output pulse of a stage upstream in the chain of the cascaded stages. An output pulse of the given stage is produced in a pull-up transistor of a push-pull amplifier. A pull-down transistor is responsive to a control signal that tracks a variation of a threshold voltage of the pull-down transistor. A difference between the control signal and the threshold voltage is maintained small in a manner to reduce a change in a conductivity of the pull-down transistor when a drift in the threshold voltage of the pull-down transistor occurs.

Abstract: A circuit, whose operating potential includes complementary pulsating signals, functions to produce quasi-static output signals which are virtually independent of the pulsations. An inverter circuit includes a first transistor connected between a first, fixed, operating voltage level and an output terminal and second and third transistors whose conduction paths are connected between the output terminal and, respectively, first and second sources of complementary pulsating signals whose voltages vary, in amplitude, between the first level and a second level. The same input signal is applied to the control electrodes of the second and third transistors whereby one of them always can, when turned on, clamp the output terminal to the second voltage level. The first transistor, when turned on, clamps the output to the first voltage level.

Abstract: Electrical contact to the substrate of a COS/MOS integrated circuit made with a four photomask process and having a well region of conductivity type opposite to that of the substrate is made by ion implanting through the bond pad openings to reconvert portions of the well to the opposite conductivity type thereby allowing contact to be made to the underlying substrate from the top surface.

Abstract: A silicon-gate insulated gate field effect transistor device has a thick field oxide in contiguous surrounding relation to its gate electrode and with a surface coplanar with or slightly higher than the surface of the gate electrode, thus facilitating crossovers and contacts to the gate electrode. The method of making this device includes forming a self-aligned silicon gate structure on a silicon wafer, masking the gate structure against the diffusion of oxygen, and thereafter oxidizing the silicon wafer to grow a thick silicon dioxide layer in surrounding relation to the silicon gate structure.

Abstract: A cascade amplifier embodying the present invention includes a plurality of amplifier stages in direct-coupled cascade connection. During specified intervals interspersed with normal amplification equal potentials are imposed on the inverting and non-inverting terminals of the first amplifier stage. A direct-coupled feedback connection from the output port of the final amplifier stage to the input port of one of the amplifier stages succeeding the first includes a sample-and-hold circuit. This sample-and-hold circuit samples the signal level appearing at the output port of the final amplifier stage during said specified intervals and holds that level for the feedback connection during the intervening periods of normal amplification to provide continuing compensation against input offset potential error.

Abstract: A complementary integrated circuit device, adapted for fabrication with relatively high circuit density, includes relatively fast transistors with a closed gate geometry. Permanently-off gates surround transistors to isolate them from other transistors.

Abstract: A circuit comprising first and second current amplifiers connected in a regenerative feedback loop and which includes a starting circuit. The latter initiates current flow in the loop and is automatically disconnected from the loop once normal operating conditions are reached therein.

Abstract: A method of making a semiconductor device which has regions of differing type and/or degree of conductivity includes the use of a multi-layer masking coating on selected regions of a body of semiconductor, and a mono-layer masking coating on other selected regions. Ion implantation together with chemical diffusion is used with a single photoresist mask to create regions of both relatively high and relatively low conductivity of one type. A second photoresist mask may be used with ion implantation and chemical diffusion to produce regions of opposite type conductivity with differing degrees of conductivity.

Abstract: A monolithic array of insulated gate field effect transistors useful, for example, as a read-only memory, has means for defining a pre-selected array of operative and non-operative transistors in a row and column arrangement. Non-operative transistors include diffused regions lying in the conductive channel zones thereof which serve to raise the value of the threshold voltage of these transistors above a value normally applied to the gate electrodes of all the transistors in the operation of the device. Operative transistors have no such threshold-raising diffused regions in their channel zones so that they can be turned on by the normally applied voltage. The array is programmable by means of a single photomask.

Abstract: Each one of two switching transistors, driven by complementary input signals, has its conduction path connected between a different one of two output terminals and a first point of potential. Connected between each output terminal and a second point of potential are the conduction paths of a load transistor responsive to the signal at the other output terminal, and an input signal responsive transistor. When the switching transistor connected to one output terminal is being turned on, the effective impedance of the input signal responsive transistor connected between that output and the second point of potential is increased, thereby increasing the speed of response of the circuit and minimizing its power dissipation.

Abstract: Unity current gain impedance transformation at the input of a field effect transistor current mirror amplifier reduces the input impedance and renders it independent of the mirror ratio. A net saving of semiconductor material may be obtained for a given mirror ratio and input impedance when the transformation is provided by a common gate connected complementary field effect transistor meeting certain effective threshold voltage and forward transfer conductance ratio requirements.

Abstract: A first field-effect transistorized constant current supply provides a first relatively constant output current. A second field-effect transistorized constant current supply is cascaded with, and driven by, the first current to provide a more highly regulated second constant output current. The system is self-starting and latch free. The second output current may be employed to drive a current mirror with a plurality of output current paths.

Abstract: Input signals lying outside the power supply range are used to develop potentials which are applied to the gate electrodes and substrates of transistors forming a transmission gate, when the transistors are to be turned off. The transmission gate circuit can then block input signals outside the range of its power supply.

Abstract: Circuits for generating pulsating potentials and voltage levels outside the range of, and/or of greater magnitude than, the operating potential applied to the circuits. Each circuit includes first and second transistors for applying a first voltage to one plate of a capacitor and a second voltage to the other plate of the capacitor, during one time interval. During a subsequent time interval, the first and second transistors are turned off and a third transistor applies the second potential to the one plate of the capacitor. The change in the potential at the one plate of the capacitor is coupled to the other plate of the capacitor at which is produced an output potential outside the range of the first and second voltages. The potential difference between the first voltage and the output potential is greater in amplitude than the potential difference between the first and second voltages.

Abstract: A counter stage comprising a static inverter and first and second dynamic inverting means. Each inverting means includes an input, an output, and means for selectively rendering the inverting means operative. The output of the first inverting means is applied to the input of the static inverter, the output of the static inverter is applied to the input of the second inverting means and the output of the second inverting means is fed back to the input of the first inverting means. When one inverting means is rendered operative, the other inverting means is rendered inoperative.

Abstract: In integrated circuit devices which have insulating coatings with portions of different thickness bounded by relatively high steps and deposited metal conductors on the coatings, yield losses often result from breaks in the metal conductors at the steps. By shaping the insulator step with an offset wherever a metal crossing is required, the probability of such breaks is reduced.