Patents by Inventor Andrew Herbert Simon
Andrew Herbert Simon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11980111Abstract: A phase change memory bridge cell comprising a dielectric layer located on top of a at least one electrode, wherein a trench is located in the dielectric layer. A first liner located at the bottom of the trench in the dielectric layer and the first liner is located on the sidewalls of the dielectric layer that forms the sidewalls of the trench. A phase change memory material located on top of the first liner, wherein a top surface of the phase change memory material is aligned with a top surface of the dielectric layer, wherein the dielectric layer is located adjacent to and surrounding the vertical sidewalls of the phase change memory material, wherein a top surface of the phase change memory material is flush with a top surface of the dielectric layer.Type: GrantFiled: September 8, 2021Date of Patent: May 7, 2024Assignee: International Business Machines CorporationInventors: Injo Ok, Andrew Herbert Simon, Kevin W. Brew, Muthumanickam Sankarapandian, Steven Michael McDermott, Nicole Saulnier
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Patent number: 11930724Abstract: A phase change memory (PCM) cell includes an electrode, a heater electrically connected to the electrode, a PCM material electrically connected to the heater, a second electrode electrically connected to the PCM material, an electrical insulator surrounding the PCM material, and a shield positioned between the PCM material and the electrical insulator, the shield comprising a reactive-ion-etching-resistant material.Type: GrantFiled: August 20, 2021Date of Patent: March 12, 2024Assignee: International Business Machines CorporationInventors: Injo Ok, Nicole Saulnier, Muthumanickam Sankarapandian, Andrew Herbert Simon, Steven Michael McDermott, Iqbal Rashid Saraf
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Publication number: 20230098562Abstract: A phase change memory (PCM) cell having a mushroom configuration includes a first electrode, a heater electrically connected to the first electrode, a first projection liner electrically connected to the heater, a PCM material electrically connected to the first projection liner, a second electrode electrically connected to the PCM material, and a second projection liner electrically connected to the first projection liner and the second electrode.Type: ApplicationFiled: September 29, 2021Publication date: March 30, 2023Inventors: Kevin W. Brew, Timothy Mathew Philip, Andrew Herbert Simon, Matthew T. Shoudy, Injo Ok
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Publication number: 20230094466Abstract: A semiconductor structure includes a substrate and a first field effect transistor (FET) formed on the substrate; the first FET includes a first FET first source-drain region, a first FET second source-drain region, a first FET gate between the first and second source-drain regions, and a first FET channel region adjacent the first FET gate and between the first FET first and second source-drain regions. Also included is a buried power rail, buried in the substrate, having a top at a level lower than the first FET channel region, and having buried power rail sidewalls. A first FET shared contact is electrically interconnected with the buried power rail and the first FET second source-drain region, and a first FET electrically isolating region is adjacent the buried power rail sidewalls and separates the buried power rail from the substrate.Type: ApplicationFiled: September 27, 2021Publication date: March 30, 2023Inventors: Julien Frougier, Nicolas Loubet, Sagarika Mukesh, PRASAD BHOSALE, Ruilong Xie, Andrew Herbert Simon, Takeshi Nogami, Lawrence A. Clevenger, Roy R. Yu, Andrew M. Greene, Daniel Charles Edelstein
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Publication number: 20230085288Abstract: A semiconductor structure includes a heater located in a first layer of a device, wherein the heater is surrounded by a dielectric, a phase change memory (PCM) liner in direct contact with a top surface of the heater in a second layer of the device, a spacer disposed adjacent the PCM liner in the second layer of the device, and a PCM stack disposed above the PCM liner in the second layer of the device.Type: ApplicationFiled: September 13, 2021Publication date: March 16, 2023Inventors: Injo Ok, Timothy Mathew Philip, Kevin W. Brew, Muthumanickam Sankarapandian, Steven Michael McDermott, Nicole Saulnier, Andrew Herbert Simon, Sanjay C. Mehta
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Publication number: 20230075622Abstract: A phase change memory bridge cell comprising a dielectric layer located on top of a at least one electrode, wherein a trench is located in the dielectric layer. A first liner located at the bottom of the trench in the dielectric layer and the first liner is located on the sidewalls of the dielectric layer that forms the sidewalls of the trench. A phase change memory material located on top of the first liner, wherein a top surface of the phase change memory material is aligned with a top surface of the dielectric layer, wherein the dielectric layer is located adjacent to and surrounding the vertical sidewalls of the phase change memory material, wherein a top surface of the phase change memory material is flush with a top surface of the dielectric layer.Type: ApplicationFiled: September 8, 2021Publication date: March 9, 2023Inventors: Injo Ok, Andrew Herbert Simon, Kevin W. Brew, Muthumanickam Sankarapandian, Steven Michael McDermott, Nicole Saulnier
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Publication number: 20230058218Abstract: A phase change memory (PCM) cell includes an electrode, a heater electrically connected to the electrode, a PCM material electrically connected to the heater, a second electrode electrically connected to the PCM material, an electrical insulator surrounding the PCM material, and a shield positioned between the PCM material and the electrical insulator, the shield comprising a reactive-ion-etching-resistant material.Type: ApplicationFiled: August 20, 2021Publication date: February 23, 2023Inventors: Injo Ok, Nicole Saulnier, Muthumanickam Sankarapandian, Andrew Herbert Simon, Steven Michael McDermott, Iqbal Rashid Saraf
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Patent number: 11476418Abstract: A semiconductor structure may include a heater surrounded by a second dielectric layer, a projection liner on top of the second dielectric layer, and a phase change material layer above the projection liner. A top surface of the projection liner may be substantially flush with a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.Type: GrantFiled: December 8, 2020Date of Patent: October 18, 2022Assignee: International Business Machines CorporationInventors: Injo Ok, Ruqiang Bao, Andrew Herbert Simon, Kevin W. Brew, Nicole Saulnier, Iqbal Rashid Saraf, Prasad Bhosale
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Patent number: 11456415Abstract: A semiconductor structure may include a heater surrounded by a dielectric layer, a projection liner on top of the heater, a phase change material layer above the projection liner, and a top electrode contact surrounding a top portion of the phase change material layer, The projection liner may cover a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer and the heater. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The top electrode contact may be separated from the phase change material layer by a metal liner. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.Type: GrantFiled: December 8, 2020Date of Patent: September 27, 2022Assignee: International Business Machines CorporationInventors: Injo Ok, Ruqiang Bao, Andrew Herbert Simon, Kevin W. Brew, Nicole Saulnier, Iqbal Rashid Saraf, Muthumanickam Sankarapandian, Sanjay C. Mehta
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Publication number: 20220181547Abstract: A semiconductor structure may include a heater surrounded by a second dielectric layer. a projection liner on top of the second dielectric layer, and a phase change material layer above the projection liner. A top surface of the projection liner may be substantially flush with a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.Type: ApplicationFiled: December 8, 2020Publication date: June 9, 2022Inventors: Injo OK, RUQIANG BAO, Andrew Herbert SIMON, Kevin W. BREW, Nicole SAULNIER, Iqbal Rashid SARAF, Prasad BHOSALE
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Publication number: 20220181546Abstract: A semiconductor structure may include a heater surrounded by a dielectric layer, a projection liner on top of the heater, a phase change material layer above the projection liner, and a top electrode contact surrounding a top portion of the phase change material layer, The projection liner may cover a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer and the heater. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The top electrode contact may be separated from the phase change material layer by a metal liner. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.Type: ApplicationFiled: December 8, 2020Publication date: June 9, 2022Inventors: Injo Ok, RUQIANG BAO, Andrew Herbert Simon, Kevin W. Brew, Nicole Saulnier, Iqbal Rashid Saraf, Muthumanickam Sankarapandian, Sanjay C. Mehta
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Patent number: 7985928Abstract: A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.Type: GrantFiled: August 13, 2008Date of Patent: July 26, 2011Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc. (“AMD”)Inventors: Tibor Bolom, Stephan Grunow, David L. Rath, Andrew Herbert Simon
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Publication number: 20090151981Abstract: A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture.Type: ApplicationFiled: August 13, 2008Publication date: June 18, 2009Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ADVANCED MICRO DEVICES INC. ("AMD")Inventors: Tibor Bolom, Stephan Grunow, David L. Rath, Andrew Herbert Simon
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Patent number: 7446036Abstract: A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.Type: GrantFiled: December 18, 2007Date of Patent: November 4, 2008Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.Inventors: Tibor Bolom, Stephan Grunow, David Rath, Andrew Herbert Simon
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Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer
Patent number: 7241696Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.Type: GrantFiled: December 11, 2002Date of Patent: July 10, 2007Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: Larry Clevenger, Timothy Joseph Dalton, Mark Hoinkis, Steffen K. Kaldor, Kaushik Kumar, Douglas C. La Tulipe, Jr., Soon-Cheon Seo, Andrew Herbert Simon, Yun-Yu Wang, Chih-Chao Yang, Haining Yang -
Patent number: 6949461Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a dielectric layer. The dielectric layer is patterned so as to expose the metal conductor. A liner layer is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor. In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer is deposited into the pattern and covers the redeposited liner layer.Type: GrantFiled: December 11, 2002Date of Patent: September 27, 2005Assignee: International Business Machines CorporationInventors: Sandra G. Malhotra, Andrew Herbert Simon
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Publication number: 20040115928Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a dielectric layer. The dielectric layer is patterned so as to expose the metal conductor. A liner layer is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor. In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer is deposited into the pattern and covers the redeposited liner layer.Type: ApplicationFiled: December 11, 2002Publication date: June 17, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sandra G. Malhotra, Andrew Herbert Simon
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Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer
Publication number: 20040115921Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.Type: ApplicationFiled: December 11, 2002Publication date: June 17, 2004Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, Infineon Technologies North America Corp.Inventors: Larry Clevenger, Timothy Joseph Dalton, Mark Hoinkis, Staffen K. Kaldor, Kaushik Kumar, Douglas C. La Tulipe, Soon-Cheon Seo, Andrew Herbert Simon, Yun-Yu Wang, Chih-Chao Yang, Haining Yang -
Publication number: 20040077140Abstract: A uniformly thick oxide film on a substrate is formed by using an anodization apparatus which deposits a blanket precursor film on a surface of a substrate; provides electrical contact to the precursor film; moves the precursor film into contact with an electrolyte solution such that substantially all electrically conductive surfaces, e.g., pin contacts, the substrate edge and a backside of the substrate are electrically isolated from the electrolyte; ensures that the surface of the precursor film on the substrate is in direct contact with the electrolyte solution; and which applies an anodizing current and/or voltage between the precursor film and a counter electrode so as to compensate for a voltage drop resulting from the presence of the electrolyte.Type: ApplicationFiled: October 16, 2002Publication date: April 22, 2004Inventors: Panayotis C. Andricacos, Roy Arthur Carruthers, Stephan Alan Cohen, John Michael Cotte, Lynne M. Gignac, Kenneth Jay Stein, Keith T. Kwietniak, Seshadri Subbanna, Horatio Seymour Wildman, David Earle Seeger, Andrew Herbert Simon
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Patent number: 6660330Abstract: The present invention relates to a method and apparatus for ensuring uniform and reproducible heating of a deformation-tolerant substrate during low-pressure chemical vapor deposition (CVD) of a metal film on a surface of the substrate. The uniform and reproducible heating of the substrate is achieved in the present invention by positioning the substrate on a beveled surface of a chamfered ring which is located above the heating element in a CVD reactor chamber. The space between heating element, chamfered ring and bottom surface of the substrate define a cavity between the substrate and heating element that ensures that the substrate is heated by radiative means rather than direct contact.Type: GrantFiled: April 10, 2001Date of Patent: December 9, 2003Assignee: International Business Machines CorporationInventors: Peter S. Locke, Sandra Guy Malhotra, Fenton Read McFeely, Andrew Herbert Simon, John Jacob Yurkas