Patents by Inventor Andrew Herbert Simon

Andrew Herbert Simon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7985928
    Abstract: A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: July 26, 2011
    Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc. (“AMD”)
    Inventors: Tibor Bolom, Stephan Grunow, David L. Rath, Andrew Herbert Simon
  • Publication number: 20090151981
    Abstract: A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture.
    Type: Application
    Filed: August 13, 2008
    Publication date: June 18, 2009
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ADVANCED MICRO DEVICES INC. ("AMD")
    Inventors: Tibor Bolom, Stephan Grunow, David L. Rath, Andrew Herbert Simon
  • Patent number: 7446036
    Abstract: A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: November 4, 2008
    Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.
    Inventors: Tibor Bolom, Stephan Grunow, David Rath, Andrew Herbert Simon
  • Patent number: 7241696
    Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: July 10, 2007
    Assignees: International Business Machines Corporation, Infineon Technologies, AG
    Inventors: Larry Clevenger, Timothy Joseph Dalton, Mark Hoinkis, Steffen K. Kaldor, Kaushik Kumar, Douglas C. La Tulipe, Jr., Soon-Cheon Seo, Andrew Herbert Simon, Yun-Yu Wang, Chih-Chao Yang, Haining Yang
  • Patent number: 6949461
    Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a dielectric layer. The dielectric layer is patterned so as to expose the metal conductor. A liner layer is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor. In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer is deposited into the pattern and covers the redeposited liner layer.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: September 27, 2005
    Assignee: International Business Machines Corporation
    Inventors: Sandra G. Malhotra, Andrew Herbert Simon
  • Publication number: 20040115928
    Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a dielectric layer. The dielectric layer is patterned so as to expose the metal conductor. A liner layer is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor. In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer is deposited into the pattern and covers the redeposited liner layer.
    Type: Application
    Filed: December 11, 2002
    Publication date: June 17, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sandra G. Malhotra, Andrew Herbert Simon
  • Publication number: 20040115921
    Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.
    Type: Application
    Filed: December 11, 2002
    Publication date: June 17, 2004
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, Infineon Technologies North America Corp.
    Inventors: Larry Clevenger, Timothy Joseph Dalton, Mark Hoinkis, Staffen K. Kaldor, Kaushik Kumar, Douglas C. La Tulipe, Soon-Cheon Seo, Andrew Herbert Simon, Yun-Yu Wang, Chih-Chao Yang, Haining Yang
  • Publication number: 20040077140
    Abstract: A uniformly thick oxide film on a substrate is formed by using an anodization apparatus which deposits a blanket precursor film on a surface of a substrate; provides electrical contact to the precursor film; moves the precursor film into contact with an electrolyte solution such that substantially all electrically conductive surfaces, e.g., pin contacts, the substrate edge and a backside of the substrate are electrically isolated from the electrolyte; ensures that the surface of the precursor film on the substrate is in direct contact with the electrolyte solution; and which applies an anodizing current and/or voltage between the precursor film and a counter electrode so as to compensate for a voltage drop resulting from the presence of the electrolyte.
    Type: Application
    Filed: October 16, 2002
    Publication date: April 22, 2004
    Inventors: Panayotis C. Andricacos, Roy Arthur Carruthers, Stephan Alan Cohen, John Michael Cotte, Lynne M. Gignac, Kenneth Jay Stein, Keith T. Kwietniak, Seshadri Subbanna, Horatio Seymour Wildman, David Earle Seeger, Andrew Herbert Simon
  • Patent number: 6661097
    Abstract: In copper backend integrated circuit technology, advanced technology using low-k organic-based interlayer dielectrics have a problem of carbon contamination that dos not occur in circuits using oxide as dielectric. A composite liner layer for the copper lines uses Ti as the bottom layer, which has the property of gettering carbon and other contaminants. The known problem with Ti of reacting with copper to form a high resistivity compound is avoided by adding a layer of TiN, which isolates the Ti and the copper.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: December 9, 2003
    Assignee: International Business Machines Corporation
    Inventors: Larry Clevenger, Stanley J. Klepeis, Hsiao-Ling Lu, Jeffrey R. Marino, Andrew Herbert Simon, Yun-Yu Wang, Kwong Hon Wong, Chih-Chao Yang
  • Patent number: 6660330
    Abstract: The present invention relates to a method and apparatus for ensuring uniform and reproducible heating of a deformation-tolerant substrate during low-pressure chemical vapor deposition (CVD) of a metal film on a surface of the substrate. The uniform and reproducible heating of the substrate is achieved in the present invention by positioning the substrate on a beveled surface of a chamfered ring which is located above the heating element in a CVD reactor chamber. The space between heating element, chamfered ring and bottom surface of the substrate define a cavity between the substrate and heating element that ensures that the substrate is heated by radiative means rather than direct contact.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: December 9, 2003
    Assignee: International Business Machines Corporation
    Inventors: Peter S. Locke, Sandra Guy Malhotra, Fenton Read McFeely, Andrew Herbert Simon, John Jacob Yurkas
  • Publication number: 20020146903
    Abstract: The present invention relates to a method and apparatus for ensuring uniform and reproducible heating of a deformation-tolerant substrate during low-pressure chemical vapor deposition (CVD) of a metal film on a surface of the substrate. The uniform and reproducible heating of the substrate is achieved in the present invention by positioning the substrate on a beveled surface of a chamfered ring which is located above the heating element in a CVD reactor chamber. The space between heating element, chamfered ring and bottom surface of the substrate define a cavity between the substrate and heating element that ensures that the substrate is heated by radiative means rather than direct contact.
    Type: Application
    Filed: April 10, 2001
    Publication date: October 10, 2002
    Applicant: International Business Machines Corporation
    Inventors: Peter S. Locke, Sandra Guy Malhotra, Fenton Read McFeely, Andrew Herbert Simon, John Jacob Yurkas
  • Patent number: 6380075
    Abstract: A method for forming an open-bottom liner for a conductor in an electronic structure and devices formed are disclosed. In the method, a pre-processed electronic substrate that has a dielectric layer on top is first provided. Via openings are then formed in a dielectric layer to expose an underlying conductive layer. The electronic substrate is then positioned in a cold-wall, low pressure chemical vapor deposition chamber, while the substrate is heated to a temperature of at least 350° C. A precursor gas is then flowed into the CVD chamber to a partial pressure of not higher than 10 mTorr, and metal is deposited from the precursor gas onto sidewalls of the via openings while bottoms of the via openings are substantially uncovered by the metal. The present invention method may be further enhanced by, optionally, modifications of a I-PVD technique or a seed layer deposition technique.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: April 30, 2002
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Chao-Kun Hu, Sandra Guy Malhotra, Fenton Read McFeely, Stephen Mark Rossnagel, Andrew Herbert Simon
  • Patent number: 6238532
    Abstract: A cooling structure and a reinforcing structure are described for use with a radio-frequency coil in an ionized physical vapor deposition apparatus. The cooling structure includes a portion for carrying coolant and is proximate to the RF coil along the outer circumference thereof. The cooling structure is shaped relative to the RF coil so that thermal expansion of the RF coil brings the RF coil into close contact with the cooling structure, thereby facilitating heat transfer from the RF coil to the coolant. The reinforcing structure is similarly shaped, and may be integrated with the cooling structure. In addition, the RF coil or cooling/reinforcing structure may be mounted to the wall of the process chamber with telescoping mounting posts, which permit the RF coil to maintain its shape while undergoing thermal expansion. The parasitic inductance of the RF coil leads is reduced by arranging those leads coaxially, thereby minimizing power losses in the RF coil.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: May 29, 2001
    Assignee: International Business Machines Corporation
    Inventors: Stephen Mark Rossnagel, Darryl D. Restaino, Andrew Herbert Simon, Pavel Smetana
  • Patent number: 6176931
    Abstract: Improvements are described for a wafer clamp ring used in an IPVD apparatus to provide cooling for the wafer clamp ring, to protect the wafer clamp ring from ion bombardment, and to prevent damage to the wafer. The wafer clamp ring is placed on a cooling fixture when not required for a deposition process. The fixture is annular in shape and in close thermal contact with a circulating coolant and is thereby cooled below ambient temperature. The cooling line and the cooling fixture are fixed relative to the IPVD device, so that problems associated with flexible cooling lines are avoided. An annular grounded shield may be provided between the plasma and clamp ring to protect the clamp ring against ion bombardment during the deposition process. The wafer clamp ring may have a portion which overhangs the wafer during a deposition process, and which has a ridge portion extending downwards therefrom and tapering to a knife edge.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: January 23, 2001
    Assignee: International Business Machines Corporation
    Inventors: Darryl D. Restaino, Stephen Mark Rossnagel, Andrew Herbert Simon, Pavel Smetana, Edward C. Cooney, III