Patents by Inventor Andrew Horch

Andrew Horch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9601203
    Abstract: A solid-state non-volatile memory (NVM) device includes a memory bit cell. The memory bit cell includes a field effect transistor (FET) fabricated on a substrate and having a floating gate. The floating gate includes a thick oxide layer. The FET includes drain and source, each fabricated within the substrate and coupled to the floating gate and a channel region with native doping. The drain is fabricated to have a halo region. A method for fabricating a solid-state NVM device includes fabricating solid state device including NVM bit cell which provides multiple storage and includes an FET on substrate. The method also includes fabricating floating gate of the FET including thick gate oxide layer, and fabricating drain and source of FET within the substrate, drain and source coupled to the floating gate and channel region with native doping. Further, the method includes fabricating halo region within the substrate at the drain.
    Type: Grant
    Filed: June 9, 2012
    Date of Patent: March 21, 2017
    Assignee: Synopsys, Inc.
    Inventors: Mads Hommelgaard, Andrew Horch, Martin Niset
  • Publication number: 20130328117
    Abstract: A solid-state non-volatile memory (NVM) device includes a memory bit cell. The memory bit cell includes a field effect transistor (FET) fabricated on a substrate and having a floating gate. The floating gate includes a thick oxide layer. The FET includes drain and source, each fabricated within the substrate and coupled to the floating gate and a channel region with native doping. The drain is fabricated to have a halo region. A method for fabricating a solid-state NVM device includes fabricating solid state device including NVM bit cell which provides multiple storage and includes an FET on substrate. The method also includes fabricating floating gate of the FET including thick gate oxide layer, and fabricating drain and source of FET within the substrate, drain and source coupled to the floating gate and channel region with native doping. Further, the method includes fabricating halo region within the substrate at the drain.
    Type: Application
    Filed: June 9, 2012
    Publication date: December 12, 2013
    Applicant: SYNOPSYS INC.
    Inventors: Mads HOMMELGAARD, Andrew HORCH, Martin NISET
  • Patent number: 7968381
    Abstract: A semiconductor device having a thyristor-based device and a pass device exhibits characteristics that may include, for example, resistance to short channel effects that occur when conventional MOSFET devices are scaled smaller in connection with advancing technology. According to an example embodiment of the present invention, the semiconductor device includes a pass device having a channel in a fin portion over a semiconductor substrate, and a thyristor device coupled to the pass device. The fin has a top portion and a side portion and extends over the semiconductor substrate. The pass device includes source/drain regions separated by the channel and a gate facing and capacitively coupled to the side portion of the fin that includes the channel. The thyristor device includes anode and cathode end portions, each end portion having base and emitter regions, where one of the emitter regions is coupled to one of the source/drain regions of the pass device.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: June 28, 2011
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Andrew Horch, Scott Robins
  • Patent number: 7374974
    Abstract: A thyristor-based semiconductor device includes a thyristor body that has at least one region in the substrate and a thyristor control port in a trenched region of the device substrate. According to an example embodiment of the present invention, the trench is at least partially filled with a dielectric material and a control port adapted to capacitively couple to the at least one thyristor body region in the substrate. In a more specific implementation, the dielectric material includes deposited dielectric material that is adapted to exhibit resistance to voltage-induced stress that thermally-grown dielectric materials generally exhibit. In another implementation, the dielectric material includes thermally-grown dielectric material, and when used in connection with highly-doped material in the trench, grows faster on the highly-doped material than on a sidewall of the trench that faces the at least on thyristor body region in the substrate.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: May 20, 2008
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Andrew Horch, Scott Robins
  • Patent number: 7351614
    Abstract: A thyristor-based semiconductor device includes a filled trench separating and electrically insulating adjacent thyristor control ports. According to an example embodiment of the present invention, the filled trench is formed in a substrate adjacent to at least one thyristor body region. The filled trench includes a conductive filler material, an insulative material formed on the conductive filler material and at least two laterally-adjacent thyristor control ports separated from one another by the conductive filler material and the insulative material. One of the control ports is adapted for capacitively coupling to the thyristor body region for controlling current in the thyristor. With this approach, two or more control ports can be formed in a single filled trench and electrically isolated by the conductive filler material/insulative material combination.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: April 1, 2008
    Assignee: T-Ram Semiconductor, Inc.
    Inventor: Andrew Horch
  • Patent number: 7320895
    Abstract: Switching operations, such as those used in memory devices, are enhanced using a thyristor-based semiconductor device adapted to switch between a blocking state and a conducting state. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor having first and second base regions coupled between first and second emitter regions, respectively. A first control port capacitively couples a first signal to the first base region, and a second control port capacitively couples a second signal to the second base region. Each of the first and second signals have a charge that is opposite in polarity, and the opposite polarity signals effect the switching of the thyristor at a lower power, relative to the power that would be required to switch the thyristor having only one control port.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: January 22, 2008
    Assignee: T-Ram Semiconductor, Inc.
    Inventors: Andrew Horch, Scott Robins, Farid Nemati
  • Patent number: 7183591
    Abstract: A semiconductor device includes a thyristor body having at least one region in a substrate. According to an example embodiment of the present invention, a trench is in a substrate and adjacent to a thyristor body region in the substrate. The trench is lined with an insulative material and further includes conductive material that is insulated from the thyristor body region in the substrate by the liner material. A conductive thyristor control port is located in the trench and adapted for capacitively coupling to the thyristor body region in the substrate and to control current in the thyristor body by causing an outflow of minority carriers in the thyristor. With this approach, conductive material can be used to fill a portion of the trench while using the trench portion including the conductive material to electrically isolate a portion of the thyristor body in the substrate.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: February 27, 2007
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Andrew Horch, Scott Robins
  • Patent number: 7135745
    Abstract: A semiconductor device having a thyristor-based device and a pass device exhibits characteristics that may include, for example, resistance to short channel effects that occur when conventional MOSFET devices are scaled smaller in connection with advancing technology. According to an example embodiment of the present invention, the semiconductor device includes a pass device having a channel in a fin portion over a semiconductor substrate, and a thyristor device coupled to the pass device. The fin has a top portion and a side portion and extends over the semiconductor substrate. The pass device includes source/drain regions separated by the channel and a gate facing and capacitively coupled to the side portion of the fin that includes the channel. The thyristor device includes anode and cathode end portions, each end portion having base and emitter regions, where one of the emitter regions is coupled to one of the source/drain regions of the pass device.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: November 14, 2006
    Assignee: T-Ram, Inc.
    Inventors: Andrew Horch, Scott Robins
  • Patent number: 7125753
    Abstract: A semiconductor memory device having a thyristor is manufactured in a manner that makes possible self-alignment of one or more portions of the thyristor. According to an example embodiment of the present invention, a gate is formed over a first portion of doped substrate. The gate is used to mask a portion of the doped substrate and a second portion of the substrate is doped before or after a spacer is formed. After the second portion of the substrate is doped, the spacer is then formed adjacent to the gate and used to mask the second portion of the substrate while a third portion of the substrate is doped. The gate and spacer are thus used to form self-aligned doped portions of the substrate, wherein the first and second portions form base regions and the third portion form an emitter region of a thyristor.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: October 24, 2006
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Andrew Horch, Scott Robins, Farid Nemati
  • Patent number: 7123508
    Abstract: A reference cell produces a reference current that is about half of the current produced by a memory cell. The reference cell is essentially the same as the memory cell with an additional current reduction device that can be a transistor. Adjusting a reference voltage applied to the transistor allows the reference current to be varied. A control circuit to produce the reference voltage includes dedicated memory and reference cells and a feedback circuit that compares the two cells' currents. The feedback circuit applies the reference voltage to the reference cell of the control circuit and adjusts the reference voltage until the current from the reference cell is about half of the current from the memory cell. The reference voltage is then applied to other reference cells in a memory array.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: October 17, 2006
    Assignee: T-RAM, Inc.
    Inventors: Andrew Horch, Tapan Samaddar
  • Publication number: 20060220120
    Abstract: LDMOS structures and methods for fabricating them includes a counter dopant implant region in a drain well. According to another aspect, an LDMOS device includes a graded junction region in the LDMOS device's channel region. The counter dopant implant region may extend from the drain portion into the graded junction region. The counter dopant implant region can be formed using an implantation process that is already part of a standard MOS fabrication process. For example, in one embodiment, an implantation process that is used to adjust the threshold voltage (Vt) is used to form the counter doped region in the channel region of the LDMOS device.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 5, 2006
    Applicant: IMPINJ, INC.
    Inventor: Andrew Horch
  • Publication number: 20060206277
    Abstract: Wirelessly testing an RFID tag before it is packaged or otherwise entered into a process reserved for “working” RFID tags is described. Various processes that employ such wireless testing as well as various “on-die” RFID tag antennae designs for facilitating the wireless testing are also described.
    Type: Application
    Filed: February 28, 2005
    Publication date: September 14, 2006
    Inventor: Andrew Horch
  • Publication number: 20060202831
    Abstract: Wirelessly testing an RFID tag before it is packaged or otherwise entered into a process reserved for “working” RFID tags is described. Various processes that employ such wireless testing as well as various “on-die” RFID tag antennae designs for facilitating the wireless testing are also described.
    Type: Application
    Filed: February 28, 2005
    Publication date: September 14, 2006
    Inventor: Andrew Horch
  • Patent number: 7064977
    Abstract: A reference cell produces a reference current that is about half of the current produced by a memory cell. The reference cell is essentially the same as the memory cell with an additional current reduction device that can be a transistor. Adjusting a reference voltage applied to the transistor allows the reference current to be varied. A control circuit to produce the reference voltage includes dedicated memory and reference cells and a feedback circuit that compares the two cells' currents. The feedback circuit applies the reference voltage to the reference cell of the control circuit and adjusts the reference voltage until the current from the reference cell is about half of the current from the memory cell. The reference voltage is then applied to other reference cells in a memory array.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: June 20, 2006
    Assignee: T-RAM, Inc.
    Inventors: Andrew Horch, Tapan Samaddar, Scott Robins
  • Publication number: 20060125507
    Abstract: Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.
    Type: Application
    Filed: December 15, 2004
    Publication date: June 15, 2006
    Inventors: John Hyde, Robert Glidden, Andrew Horch, Jay Kuhn, Ronald Oliver
  • Patent number: 7053423
    Abstract: A thyristor-based semiconductor device exhibits a relatively increased base-emitter capacitance. According to an example embodiment of the present invention, a base region and an adjacent emitter region of a thyristor are doped such that the emitter region has a lightly-doped portion having a light dopant concentration, relative to the base region. In one embodiment, the thyristor is implemented in a memory circuit, wherein the emitter region is coupled to a reference voltage line and a control port is arranged for capacitively coupling to the thyristor for controlling current flow therein. In another implementation, the thyristor is formed on a buried insulator layer of a silicon-on-insulator (SOI) structure. With these approaches, current flow in the thyristor, e.g., for data storage therein, can be tightly controlled.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: May 30, 2006
    Assignee: T-RAM, Inc.
    Inventors: Farid Nemati, Scott Robins, Andrew Horch
  • Patent number: 7049182
    Abstract: A semiconductor device is formed having a thyristor, a pass device and a conductive shunt that electrically connects an emitter region of the thyristor with a node near an upper surface of the substrate. In one example embodiment of the present invention, the conductive shunt is formed in a trench in a substrate and extending from an upper surface of the substrate to an emitter region of a vertical thyristor, with the emitter region being in the substrate and below the upper surface. In one implementation, the thyristor includes a thyristor body and a control port, with an N+ emitter region of the thyristor body being in the substrate and below and upper surface thereof. A pass device is formed adjacent to the thyristor, and the conductive shunt is formed in a trench extending from the N+ emitter region to a source/drain region of the pass device.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: May 23, 2006
    Assignee: T-RAM, Inc.
    Inventors: Andrew Horch, Scott Robins
  • Patent number: 7030425
    Abstract: A semiconductor device includes a thyristor having at least one body region thereof disposed in a substrate, and a filled trench having a conductive material. According to an example embodiment of the present invention, a conductive material having a narrow upper portion over a relatively wide lower portion is in a filled trench adjacent to at least one thyristor body region in a substrate. In one implementation, a thyristor control port is located over the wide lower portion and adjacent to the narrow upper portion of the conductive shunt and is adapted for capacitively coupling to the thyristor body region in the substrate for controlling current in the thyristor. In another implementation, the conductive material is electrically coupled to a buried emitter region of the thyristor and arranged for shunting current between the buried emitter region and a circuit node near an upper portion of the conductive material.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: April 18, 2006
    Assignee: TRAM, Inc.
    Inventors: Andrew Horch, Scott Robins
  • Patent number: 7015077
    Abstract: A semiconductor device is formed having a thyristor and trench arranged to electrically insulate an emitter region of the thyristor from another circuit structure. In one example embodiment of the present invention, a trench having a bottom portion with two different trench depths is etched in the substrate. A thyristor is formed having a control port in a trench and having an emitter region adjacent to the trench and below an upper surface of the substrate. A deeper portion of the trench electrically insulates the emitter region from the other circuit structure. The control port is capacitively coupled to the thyristor and to the other circuit structure (e.g., in response to at least one edge of a voltage pulse applied thereto). In one implementation, the trench further includes an emitter-access connector extending from the emitter region to an upper surface of the substrate.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: March 21, 2006
    Assignee: T-RAM, Inc.
    Inventors: Andrew Horch, Scott Robins
  • Patent number: 6998652
    Abstract: A semiconductor device includes a thyristor body having at least one region in a substrate. According to an example embodiment of the present invention, a trench is in a substrate and adjacent to a thyristor body region in the substrate. The trench is lined with an insulative material and further includes conductive material that is insulated from the thyristor body region in the substrate by the liner material. A conductive thyristor control port is located in the trench and adapted for capacitively coupling to the thyristor body region in the substrate and to control current in the thyristor body by causing an outflow of minority carriers in the thyristor. With this approach, conductive material can be used to fill a portion of the trench while using the trench portion including the conductive material to electrically isolate a portion of the thyristor body in the substrate.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: February 14, 2006
    Assignee: T-Ram, Inc.
    Inventors: Andrew Horch, Scott Robins