Patents by Inventor Andrew James Brown
Andrew James Brown has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953529Abstract: Position sensing modules associated with a device are provided. The position sensing modules are configured to receive electrical characteristics associated with one or more switches of a device over a predetermined period of time, the one or more switches being configured to connect service to or disconnect service from a customer; calculate a match indicator for each phase of the device including the one or more switches, the match indicator indicating whether an electrical characteristic on a load-side of the device matches a same electrical characteristic on a line-side of the device for each phase of the device; and determine a position of the one or more switches based on the received electrical characteristics and the calculated match indicator for each phase of the device.Type: GrantFiled: March 5, 2020Date of Patent: April 9, 2024Assignee: Sensus Spectrum, LLCInventors: Matthew James Savarda, Michael Ray Brown, Andrew James Bryce Dudding
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Publication number: 20240103053Abstract: Position sensing and verification modules and a meter are provided. A module is configured to determine a position of one or more switch poles by measuring a current across the one or more switch poles. If a current is greater than or equal to a predetermined current threshold, the position is closed. If a current is less than the predetermined current threshold, the position is open. The module is configured to determine a line voltage with respect to a first reference value, determine a load voltage with respect to the first reference value, compare the line voltage to the load voltage to determine if the line voltage and the load voltage are within a predetermined threshold, and confirm the position of the one or more switch poles based on the comparison of the line voltage to the load voltage for the one or more line phases.Type: ApplicationFiled: December 6, 2023Publication date: March 28, 2024Inventors: Matthew James Savarda, Michael Ray Brown, Andrew James Bryce Dudding
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Patent number: 11830809Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a magnetic structure around the conductive line, and material stubs at side faces of the magnetic structure.Type: GrantFiled: March 25, 2020Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Ying Wang, Yikang Deng, Junnan Zhao, Andrew James Brown, Cheng Xu, Kaladhar Radhakrishnan
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Publication number: 20230345621Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a dielectric layer, in a substrate, the dielectric layer including an electroless catalyst, wherein the electroless catalyst includes one or more of palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, and tantalum; a first conductive trace having a first thickness in the dielectric layer, wherein the first thickness is between 4 um and 143 um; and a second conductive trace having a second thickness in the dielectric layer, wherein the second thickness is between 2 um and 141 um, wherein the first thickness is greater than the second thickness, and wherein the first conductive trace and the second conductive trace have sloped sidewalls.Type: ApplicationFiled: June 30, 2023Publication date: October 26, 2023Applicant: Intel CorporationInventors: Brandon C. Marin, Andrew James Brown, Rahul Jain, Dilan Seneviratne, Praneeth Kumar Akkinepally, Frank Truong
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Patent number: 11737208Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) and an electroless catalyst; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the first thickness is greater than the second thickness.Type: GrantFiled: February 6, 2019Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Brandon C. Marin, Andrew James Brown, Rahul Jain, Dilan Seneviratne, Praneeth Kumar Akkinepally, Frank Truong
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Patent number: 11552008Abstract: Disclosed herein are asymmetric cored integrated circuit (IC) package supports, and related devices and methods. For example, in some embodiments, an IC package support may include a core region having a first face and an opposing second face, a first buildup region at the first face of the core region, and a second buildup region at the second face of the core region. A thickness of the first buildup region may be different than a thickness of the second buildup region. In some embodiments, an inductor may be included in the core region.Type: GrantFiled: November 28, 2018Date of Patent: January 10, 2023Assignee: Intel CorporationInventors: Lauren Ashley Link, Andrew James Brown, Prithwish Chatterjee, Sai Vadlamani, Ying Wang, Chong Zhang
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Publication number: 20220332130Abstract: A sheet 200 for an array of vacuum apertures 152 in a substrate support unit 150 of a printer is provided. The sheet 200 comprises a plurality of valves 202 formed into the sheet 200. The sheet 200 is made from a resilient material. Each valve 202 comprises a valve head 204 for sealing a vacuum aperture 152 in the substrate support unit 150, and a valve lever arm 206 for permitting movement of the valve head 204 towards and away from the vacuum aperture 152 in order to open and close the valve 202.Type: ApplicationFiled: April 14, 2022Publication date: October 20, 2022Applicant: Inca Digital Printers LimitedInventors: Andrew James Brown, Anderson McKeague
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Publication number: 20220332510Abstract: A substrate support system 10 for a conveyor printer is provided, comprising a support unit 100 comprising a plurality of vacuum apertures 108 arranged for fluidic communication with a source of negative pressure. The support unit 100 also comprises at least one air bearing 114 arranged for fluidic communication with a source of positive pressure. The air bearing 114 comprises porous media 116. The substrate support system 10 also comprises a conveyor belt 150 arranged over the support unit 100 for supporting a substrate 170 to be printed on. The conveyor belt 150 comprises a plurality of belt apertures. The vacuum apertures 108 are arranged to convey a negative pressure through the belt apertures for retaining the substrate 170 on the conveyor belt 150. The at least one air bearing 114 is arranged to convey a positive pressure to support the conveyor belt 150.Type: ApplicationFiled: April 14, 2022Publication date: October 20, 2022Applicant: Inca Digital Printers LimitedInventors: Andrew James Brown, Anderson McKeague
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Patent number: 11444042Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line and a magnetic structure around a top surface of the conductive line and side surfaces of the conductive line. The magnetic structure may have a tapered shape that narrows toward the conductive line.Type: GrantFiled: June 5, 2018Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Andrew James Brown, Ying Wang, Chong Zhang, Lauren Ashley Link, Yikang Deng
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Publication number: 20220278038Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.Type: ApplicationFiled: May 12, 2022Publication date: September 1, 2022Applicant: Intel CorporationInventors: Ji Yong Park, Kyu Oh Lee, Yikang Deng, Zhichao Zhang, Liwei Cheng, Andrew James Brown, Cheng Xu, Jiwei Sun
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Patent number: 11380609Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.Type: GrantFiled: May 21, 2018Date of Patent: July 5, 2022Assignee: Intel CorporationInventors: Cheng Xu, Jiwei Sun, Ji Yong Park, Kyu Oh Lee, Yikang Deng, Zhichao Zhang, Liwei Cheng, Andrew James Brown
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Publication number: 20210305154Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a magnetic structure around the conductive line, and material stubs at side faces of the magnetic structure.Type: ApplicationFiled: March 25, 2020Publication date: September 30, 2021Applicant: Intel CorporationInventors: Ying Wang, Yikang Deng, Junnan Zhao, Andrew James Brown, Cheng Xu, Kaladhar Radhakrishnan
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Patent number: 11075130Abstract: Semiconductor packages including package substrates having polymer-derived ceramic cores are described. In an example, a package substrate includes a core layer including a polymer-derived ceramic. The polymer-derived ceramic may include filler particles to control shrinkage and reduce warpage of the core layer during fabrication and use of the package substrate. The core layer may include counterbores or blind holes to embed a contact pad or an electrical interconnect in the core layer. A semiconductor die may be mounted on the package substrate and may be electrically connected to the contact pad or the electrical interconnect.Type: GrantFiled: March 30, 2017Date of Patent: July 27, 2021Assignee: Intel CorporationInventors: Lisa Ying Ying Chen, Lauren Ashley Link, Robert Alan May, Amruthavalli Pallavi Alur, Kristof Kuwawi Darmawikarta, Siddharth K. Alur, Sri Ranga Sai Boyapati, Andrew James Brown, Lilia May
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Publication number: 20200253037Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) and an electroless catalyst; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the first thickness is greater than the second thickness.Type: ApplicationFiled: February 6, 2019Publication date: August 6, 2020Applicant: Intel CorporationInventors: Brandon C. Marin, Andrew James Brown, Rahul Jain, Dilan Seneviratne, Praneeth Kumar Akkinepally, Frank Truong
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Publication number: 20200168536Abstract: Disclosed herein are asymmetric cored integrated circuit (IC) package supports, and related devices and methods. For example, in some embodiments, an IC package support may include a core region having a first face and an opposing second face, a first buildup region at the first face of the core region, and a second buildup region at the second face of the core region. A thickness of the first buildup region may be different than a thickness of the second buildup region. In some embodiments, an inductor may be included in the core region.Type: ApplicationFiled: November 28, 2018Publication date: May 28, 2020Applicant: Intel CorporationInventors: Lauren Ashley Link, Andrew James Brown, Prithwish Chatterjee, Sai Vadlamani, Ying Wang, Chong Zhang
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Publication number: 20190393109Abstract: Semiconductor packages including package substrates having polymer-derived ceramic cores are described. In an example, a package substrate includes a core layer including a polymer-derived ceramic. The polymer-derived ceramic may include filler particles to control shrinkage and reduce warpage of the core layer during fabrication and use of the package substrate. The core layer may include counterbores or blind holes to embed a contact pad or an electrical interconnect in the core layer. A semiconductor die may be mounted on the package substrate and may be electrically connected to the contact pad or the electrical interconnect.Type: ApplicationFiled: March 30, 2017Publication date: December 26, 2019Inventors: Lisa Ying Ying CHEN, Lauren Ashley LINK, Robert Alan MAY, Amruthavalli Pallavi ALUR, Kristof Kuwawi DARMAWIKARTA, Siddharth K. ALUR, Sri Ranga Sai BOYAPATI, Andrew James BROWN, Lilia MAY
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Publication number: 20190371744Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line and a magnetic structure around a top surface of the conductive line and side surfaces of the conductive line. The magnetic structure may have a tapered shape that narrows toward the conductive line.Type: ApplicationFiled: June 5, 2018Publication date: December 5, 2019Applicant: Intel CorporationInventors: Andrew James Brown, Ying Wang, Chong Zhang, Lauren Ashley Link, Yikang Deng
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Publication number: 20190355654Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.Type: ApplicationFiled: May 21, 2018Publication date: November 21, 2019Applicant: Intel CorporationInventors: Cheng Xu, Jiwei Sun, Ji Yong Park, Kyu Oh Lee, Yikang Deng, Zhichao Zhang, Liwei Cheng, Andrew James Brown
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Patent number: 8152414Abstract: A device and method for the reduction of vortex-induced vibration of a deepwater riser. A device for attachment to a structure, which is subject to movement relative to a fluid surrounding the structure, for reducing vortex-induced vibration effects on the structure, the device comprising: a flexible netting (4) interconnecting a plurality of relatively inflexible members comprising a plurality of elongate members (3) and a plurality of spacer members (6), wherein each elongate member has a first cuter boundary and each spacer member has a second outer boundary wherein the second boundary extends radially outward of the first outer boundary relative to the netting, over at least: a substantial portion of the boundary.Type: GrantFiled: April 25, 2008Date of Patent: April 10, 2012Inventor: Andrew James Brown
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Patent number: D1015966Type: GrantFiled: March 26, 2021Date of Patent: February 27, 2024Assignee: ARB CORPORATION LTDInventors: Gavin James Colgan-Smith, John Desmond Clark, Andrew Harry Brown