Abstract: A memory device and system are disclosed that may include a serial data interface, a serial address interface, and a reference clock interface. The reference clock interface is configured to receive a signal from a reference clock source that provides a reference clock signal to a memory control device. The serial interfaces are coupled to other memory devices or memory control devices. A method of transferring data within a memory system using serial interfaces is also disclosed. The method includes performing clock multiplication on a reference clock to provide a multiplied clock, using the multiplied clock to serialize and transmit data onto a serial interface, recovering data from the seal interface, using the reference clock to determine an initial frequency for use by clock and data recovery module, using the data recovered from the serial interface to determine a phase and final frequency of a recovered clock, and using the recovered clock to de-serialize received serial data into parallel data words.

Abstract: The present disclosure is generally directed to a method of communicating data between two or more semiconductor devices. Serial interfaces using the method have a reduction in latency compared to conventional serial interfaces. The method enables features needed for a serial interface, such as limited run lengths and recognizable data boundaries to establish alignment. In addition, a method for synchronizing two or more semiconductor devices through serial interfaces has been presented. This is done by passing a marker data pattern through the system.

Abstract: A memory device and system are disclosed that may include a serial data interface, a serial address interface, and a reference clock interface. The reference clock interface is configured to receive a signal from a reference clock source that provides a reference clock signal to a memory control device. The serial interfaces are coupled to other memory devices or memory control devices. A method of transferring data within a memory system using serial interfaces is also disclosed. The method includes performing clock multiplication on a reference clock to provide a multiplied clock, using the multiplied clock to serialize and transmit data onto a serial interface, recovering data from the seal interface, using the reference clock to determine an initial frequency for use by clock and data recovery module, using the data recovered from the serial interface to determine a phase and final frequency of a recovered clock, and using the recovered clock to de-serialize received serial data into parallel data words.

Abstract: A system for managing content and work items in a plurality of disparate content repositories and workflow systems. The first module organizes content, content organizing structures, work items, and/or work organizing structures into virtual repositories. The second module provides access to workflow in disparate workflow systems having a plurality of proprietary program interfaces. The third module creates rich relationships between two or more pieces of content, content organizing structures, work items and/or work organizing structures that exist in a plurality of content repositories, workflow systems and/or other external information sources.

Abstract: A tissue treatment system has a handheld treatment instrument that generates a gas plasma jet for delivering thermal energy to a tissue surface to be treated. Incorporated in the handpiece is an optical target marking projector for projecting a visible target marker onto the tissue surface when spaced from a distal end of the handpiece. The marker indicates a treatment area and is generated by illuminating an apertured mask and transmitting light from the mask via an optical fibre guide to an exit aperture adjacent a gas plasma nozzle of the instrument. A method regenerates the reticular architecture of tissue whilst illuminating the treatment area using the target marker.

Abstract: A programmable logic device includes a plurality of programmable multi-gigabit transceivers, programmable logic fabric, and a control module. Each of the plurality of programmable multi-gigabit transceivers is individually programmed to a desired transceiving mode of operation in accordance with a plurality of transceiver settings. The programmable logic fabric is operably coupled to the plurality of programmable multi-gigabit transceivers and is configured to process at least a portion of the data being transceived via the multi-gigabit transceivers. The control module is operably coupled to produce the plurality of transceiver settings based on a desired mode of operation for the programmable logic device.

Abstract: A method and apparatus for tracking and controlling one or more voltage and current supplies during a transition between and off-state to an on-state, or from an on state to an off-state, is enabled by detecting a voltage or current transition and controlling the voltage or current supply transition within a specified upper and lower limit about a reference transition.

Abstract: A circuit for providing programmable hysteresis levels is disclosed. The circuit includes comparators for producing output signals when an input signal crosses respective set points and a hysteresis circuit for establishing a hysteresis in the output signals. When a comparator's output signal is "on", the input signal is shifted by a hysteresis differential. The output signal is terminated when the shifted input signal returns to the set point. The hysteresis circuit includes a programmable hysteresis input for adjusting the hysteresis differential to different preset and intermediate hysteresis levels.

Abstract: A method for providing programmable hysteresis levels includes producing output signals when an input signal crosses respective set points and establishing a hysteresis in the output signals. When a comparator's output signal is "on", the input signal is shifted by a hysteresis differential. The output signal is terminated when the shifted input signal returns to the set point. A programmable hysteresis input is adjusted to set the hysteresis differential to different preset and intermediate hysteresis levels.