Abstract: The present invention provides a look ahead architecture to satisfy the retransmit recovery time constraints in a mark and retransmit system while allowing a full bitline precharge. A number of sense amplifiers are provided in the look ahead architecture that may be equipped with a "shadow latch" to store the read data when the mark pointer is asserted. As a result, the data to be retransmitted will be retrieved from the shadow latches when the retransmit is asserted, allowing a full precharge cycle before reading from the memory array.

Abstract: A circuit and method for generating a global write enable signal for use in an SRAM partitioning scheme. The global write enable signal is generated by taking a combination of the individual write enable signals and presenting them as a global write control. The global write control signal allows all of the particular data groups to have common timing. The particular SRAM data groups may implement configuration dependent functionality which can be grouped with other data partitions in the array. A particular SRAM data group may share local decode and write control circuitry with other data groups. Particular SRAM data groups not selected for writing have their write data inputs driven to an inactive state during the WRITE.

Abstract: The present invention provides a circuit for generating a programmable write-read word line equality signal in FIFO buffers. The present invention significantly reduces the gate delay associated in producing the write-read word line equality signal. The delay is reduced from a typical 30-50 gate delays, to as little as four gate delays. The present invention accomplishes this by processing several bit operations in parallel and making the general circuit architecture symmetric. The delay is constant in all of the parallel paths but amounts to only a short delay for the final WREQ output.

Abstract: The present invention provides an efficient design that can be used to generate a programmable almost empty or programmable almost full flags. The present invention accomplishes this by efficiently evaluating the read count minus write count plus a user programmed offset being greater than or equal to zero for the programmable almost empty flag generation. Similarly, evaluating write count minus the read count plus the user programmed offset minus the size of the FIFO is greater than or equal to zero for the programmable almost full flag generation. The counters in the FIFO count from 0 to twice the size of the FIFO minus one and the user programmed offset can be between 0 to the size of the FIFO minus one. The offset has one less bit than the read and write counters. The processing block masks out the higher order bits of the Offset input based on the size of the FIFO. The first stage performs the bit wise addition of the offset, read counter and write counter inputs without any carry chain propagation.

Abstract: The invention concerns an asynchronous state machine with a programmable tSKEW which may be used to generate a half-empty and half-full flags in a synchronous FIFO buffer. The present invention may reduce the delay associated in producing the half-full or half-empty flags from a typical eight gate delays, to as little as no gate delays. The reduction may be accomplished by using a first state machine which can make an internal flag go low, or active, and a second state machine which can make the internal flag go high, or inactive. The functioning of the first and second state machines may be controlled by a blocking logic. The output of each of the state machines may be stored in a latch. The output of the latch may be presented to an input of the blocking logic, which may be used by the blocking logic to control the activity of the state machines.

Abstract: The present invention concerns a method and apparatus for disabling columns using a local fuse decoding system. The present invention uses local decoding in order to use a number of fuses that is less than the number of columns in order to disable column failures. This is particularly useful when the fuse pitch is greater than the column pitch which does not allow for a fuse to be implemented in each column.

Abstract: A state machine design which can be used to realize extremely short flag generation delays, also realizing the benefit of having an extremely high MTBF. A set of next state variables are generated from a combination of three previous state variables and three additional inputs representing a logical "OR" of a read half-full and write half-full flag WRH, an external write clock input, and an external read clock input. The next state variables are derived from a product of the previous state variables, a complement signal of the previous state variables, and the signal WRH. The half-full flag is generated using digital logic decoding techniques that manipulate inputs from the three next state variables, a read clock signal and a write clock signal.

Abstract: A FIFO (First-In-First-Out) memory includes a main memory array and a main select circuit having a plurality of serially coupled shift registers, each selecting at least one memory location of the main memory array. The FIFO memory also includes a redundant memory array and a redundant select circuit having a plurality of redundant shift registers, each selecting at least one redundant memory location of the redundant memory array. A switching circuit is provided in the FIFO memory that is coupled to each of the shift registers and each of the redundant shift registers. When a memory location of the main memory is found defective, the switching circuit causes a corresponding shift register of the shift registers to be bypassed in the main select circuit and a redundant shift register of the redundant shift registers to be serially coupled into the main select circuit via a last one of the shift registers.

Abstract: The present invention concerns data transition method and apparatus for driving a set of write data signals to an inactive (or deasserted) state upon completion of a WRITE to a particular group of memory cells. The present invention drives the write data signals to a an inactive state to end a WRITE without waiting for the end of the write control pulse. The present invention triggers a group of data write buffers to drive one of the write data signals to a "0" at the beginning of the WRITE control pulse or at a data input transition during a WRITE. A delayed transition of the write data signals may be used to drive both the write data signals to a "1"? to end the WRITE within a particular memory group. The write data transition detection is accomplished at the write data inputs of the groups of memory cells without relying on global chip data input pin transition detection and pulse width setting.

Abstract: A state machine for generating a flag that represents the fullness of a FIFO buffer is disclosed. The present invention generates a set of next state variables that are derived generally from a combination of three previous state variables and three additional inputs representing an internally generated look-ahead flag, an external write clock and an external read clock. The next state variables are derived specifically from a product of the previous state variables and complement signals of the previous state variables. The full flag is generated using digital logic decoding techniques that manipulate inputs from the three next state variables, a read clock signal and a write clock signal and a look-ahead decoded internal full flag signal. An empty flag can be generated by switching the read and write clock inputs and changing the look-ahead decoded internal full flag to a look-ahead decoded internal empty flag.

Abstract: A method and apparatus for writing data onto the read bitline when a FIFO buffer memory is nearly empty that includes circuitry detecting when a memory is nearly empty, when the read pointer and the write pointer are on the same line with the read pointer behind the write pointer. Another circuit writes data onto the read bitline as the data is written into the buffer memory.

Abstract: The present invention provides a circuit and method for manipulating the least significant bit (LSB) of the read and write count signal to generate a glitch free mutually non-exclusive decoder output. The present invention can be used to generate a logic to eliminate glitches in the inputs to a full/empty flag generator, an almost full/almost empty flag generator or a half-full/half-empty flag generator. The circuit can be extended to generate the logic to eliminate glitches in either direction as the count signals move across a boundary change in a half-full flag generation circuit.

Abstract: The present invention provides a system for testing a memory array and corresponding support circuitry. The present invention provides a highly efficient testing mode to be entered that allows any type of advanced testing to be performed on the memory array without regard to the restrictions imposed by the various status flags that may be present. The testing mode can be entered by a completely user-defined mechanism. During this testing mode, the user has complete control over the contents of the memory array and can also have complete control over the positioning of the write word line with respect to the read word line without, for example, any write-read word line pointer equality signals being generated. In one example of the present invention used in a FIFO, testing times required for data retention testing are reduced from approximately six seconds to approximately 500.mu.

Abstract: The invention describes an asynchronous state machine with a programmable tSKEW that is used to generate an empty and full flag in a synchronous FIFO buffer. The present invention reduces the delay associated in producing the full or empty flags from a typical eight gate delays, to as little as no gate delays. The present invention accomplishes this by using a set state machine which can only make an internal flag go low, or active, and a reset state machine which can only make the internal flag go high, or inactive. The functioning of the set state machine and the reset state machine is controlled by a blocking logic. The output of each of the state machines is stored in a latch. The output of the latch is presented to an input of the blocking logic, which is used by the blocking logic to control the activity of the state machines.