Patents by Inventor Andrew M. Jones

Andrew M. Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240123115
    Abstract: A solidifying prepolymeric implant composition comprising a biocompatible prepolymer and an optional filler. One such implant composition is a polyurethane implant composition comprising an isocyanate, such as hydroxymethylenediisocyanate (HMDI) and an alcohol, such as polycaprolactonediol (PCL diol). The compositions of the invention are useful for improving bone structure in patients by applying the solidifying implant composition to bone, reinforcing bone structure, improving load bearing capacity and/or aiding healing of microfractures.
    Type: Application
    Filed: December 23, 2023
    Publication date: April 18, 2024
    Applicant: 206 ORTHO, INC.
    Inventors: Jeffrey A. D'Agostino, Andrew J. CARTER, Craig M. Jones, Arthur Watterson
  • Publication number: 20240123452
    Abstract: Systems, methods, and apparatuses are provided for self-contained nucleic acid preparation, amplification, and analysis.
    Type: Application
    Filed: May 19, 2023
    Publication date: April 18, 2024
    Inventors: Kirk M. Ririe, Aaron D. Wernerehl, Christopher P. Pasko, Ali Laayoun, Carole Vachon, Agnès Dupont-Filliard, Laurent Mesta, Andrew C. Hatch, Erik W. Huynh, David E. Jones
  • Patent number: 11699615
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: July 11, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Lu Fei, Jeffrey L. Libbert, Andrew M. Jones, Alex Usenko, Gang Wang, Shawn George Thomas, Srikanth Kommu
  • Publication number: 20230072964
    Abstract: A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).
    Type: Application
    Filed: October 18, 2022
    Publication date: March 9, 2023
    Inventors: Igor Peidous, Andrew M Jones, Srikanth Kommu, Horacio Josue Mendez
  • Patent number: 11508612
    Abstract: A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 22, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Andrew M Jones, Srikanth Kommu, Horacio Josue Mendez
  • Patent number: 11402624
    Abstract: Electrowetting-actuated optical shutters based on total internal reflection or beam steering. An electrowetting cell contains a conducting liquid and a non-conducting liquid configured to form a liquid-liquid interface extending to the inner walls of the cell. A beam of light is directed to the liquid-liquid interface at an angle near the total internal reflection angle of the interface. Voltage changes the shape of the liquid-liquid interface, without separating it from the inner walls of the cell. Thus, when depending on the voltage applied, the beam is either transmitted in part or substantially totally internal reflected.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: August 2, 2022
    Assignee: Regents of the University of Colorado
    Inventors: Juliet T. Gopinath, Victor M. Bright, Andrew M. Jones
  • Publication number: 20210384070
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
    Type: Application
    Filed: August 25, 2021
    Publication date: December 9, 2021
    Inventors: Igor Peidous, Lu Fei, Jeffrey L. Libbert, Andrew M. Jones, Alex Usenko, Gang Wang, Shawn George Thomas, Srikanth Kommu
  • Patent number: 11145538
    Abstract: A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: October 12, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Jeffery L. Libbert, Qingmin Liu, Gang Wang, Andrew M. Jones
  • Patent number: 11139198
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 5, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Lu Fei, Jeffrey L. Libbert, Andrew M. Jones, Alex Usenko, Gang Wang, Shawn George Thomas, Srikanth Kommu
  • Publication number: 20200183147
    Abstract: Electrowetting-actuated optical shutters based on total internal reflection or beam steering. An electrowetting cell contains a conducting liquid and a non-conducting liquid configured to form a liquid-liquid interface extending to the inner walls of the cell. A beam of light is directed to the liquid-liquid interface at an angle near the total internal reflection angle of the interface. Voltage changes the shape of the liquid-liquid interface, without separating it from the inner walls of the cell. Thus, when depending on the voltage applied, the beam is either transmitted in part or substantially totally internal reflected.
    Type: Application
    Filed: February 13, 2020
    Publication date: June 11, 2020
    Inventors: Juliet T. Gopinath, Victor M. Bright, Andrew M. Jones
  • Publication number: 20200126846
    Abstract: A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).
    Type: Application
    Filed: December 19, 2019
    Publication date: April 23, 2020
    Inventors: Igor Peidous, Andrew M. Jones, Srikanth Kommu, Horacio Josue Mendez
  • Patent number: 10622247
    Abstract: A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel includes a charge trapping layer (CTL).
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: April 14, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Andrew M Jones, Srikanth Kommu, Horacio Josue Mendez
  • Patent number: 10598919
    Abstract: Electrowetting-actuated optical shutters based on total internal reflection or beam steering. An electrowetting cell contains a conducting liquid and a non-conducting liquid configured to form a liquid-liquid interface extending to the inner walls of the cell. A beam of light is directed to the liquid-liquid interface at an angle near the total internal reflection angle of the interface. Voltage changes the shape of the liquid-liquid interface, without separating it from the inner walls of the cell. Thus, when depending on the voltage applied, the beam is either transmitted in part or substantially totally internal reflected.
    Type: Grant
    Filed: March 5, 2017
    Date of Patent: March 24, 2020
    Assignee: The Regents of the University of Colorado
    Inventors: Juliet T. Gopinath, Victor M. Bright, Andrew M. Jones
  • Publication number: 20200027778
    Abstract: A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 23, 2020
    Inventors: Jeffery L. Libbert, Qingmin Liu, Gang Wang, Andrew M. Jones
  • Patent number: 10483152
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: November 19, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Lu Fei, Jeffrey L. Libbert, Andrew M. Jones, Alex Usenko, Gang Wang, Shawn George Thomas, Srikanth Kommu
  • Patent number: 10468294
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: November 5, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Andrew M. Jones, Srikanth Kommu, Gang Wang, Jeffrey L. Libbert
  • Patent number: 10468295
    Abstract: A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: November 5, 2019
    Assignee: GLOBALWAFERS CO. LTD.
    Inventors: Jeffery L. Libbert, Qingmin Liu, Gang Wang, Andrew M. Jones
  • Patent number: 10381260
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: August 13, 2019
    Assignee: GlobalWafers Co., Inc.
    Inventors: Igor Peidous, Jeffrey L. Libbert, Srikanth Kommu, Andrew M. Jones, Samuel Christopher Pratt, Horacio Josue Mendez, Leslie George Stanton, Michelle Rene Dickinson
  • Publication number: 20190139818
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Igor Peidous, Lu Fei, Jeffrey L. Libbert, Andrew M. Jones, Alex Usenko, Gang Wang, Shawn George Thomas, Srikanth Kommu
  • Publication number: 20190080957
    Abstract: A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).
    Type: Application
    Filed: February 14, 2017
    Publication date: March 14, 2019
    Inventors: Igor Peidous, Andrew M Jones, Srikanth Kommu, Horacio Josue Mendez