Abstract: A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.

Abstract: A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer.

Abstract: A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

Abstract: Electrowetting-actuated optical shutters based on total internal reflection or beam steering. An electrowetting cell contains a conducting liquid and a non-conducting liquid configured to form a liquid-liquid interface extending to the inner walls of the cell. A beam of light is directed to the liquid-liquid interface at an angle near the total internal reflection angle of the interface. Voltage changes the shape of the liquid-liquid interface, without separating it from the inner walls of the cell. Thus, when depending on the voltage applied, the beam is either transmitted in part or substantially totally internal reflected.

Abstract: A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

Abstract: Apparatus, systems, and methods using an optically pumped gas filled hollow fiber laser can be implemented in a variety of applications. In various embodiments, operation of an optically pumped gas filled hollow fiber laser is based on population inversion in the gas. Additional apparatus, systems, and methods are disclosed.

Abstract: Methods and systems are disclosed for performing a passivation process on a silicon-on-insulator wafer in a chamber in which the wafer is cleaved. A bonded wafer pair is cleaved within the chamber to form the silicon-on-insulator (SOI) wafer. A cleaved surface of the SOI wafer is then passivated in-situ by exposing the cleaved surface to a passivating substance. This exposure to a passivating substance results in the formation of a thin layer of oxide on the cleaved surface. The silicon-on-insulator wafer is then removed from the chamber. In other embodiments, the silicon-on-insulator wafer is first transferred to an adjoining chamber where the wafer is then passivated. The wafer is transferred to the adjoining chamber without exposing the wafer to the atmosphere outside the chambers.

Abstract: Apparatus, systems, and methods using an optically pumped gas filled hollow fiber laser can be implemented in a variety of applications. In various embodiments, operation of an optically pumped gas filled hollow fiber laser is based on population inversion in the gas. Additional apparatus, systems, and methods are disclosed.

Abstract: Methods and systems are disclosed for performing a passivation process on a silicon-on-insulator wafer in a chamber in which the wafer is cleaved. A bonded wafer pair is cleaved within the chamber to form the silicon-on-insulator (SOI) wafer. A cleaved surface of the SOI wafer is then passivated in-situ by exposing the cleaved surface to a passivating substance. This exposure to a passivating substance results in the formation of a thin layer of oxide on the cleaved surface. The silicon-on-insulator wafer is then removed from the chamber. In other embodiments, the silicon-on-insulator wafer is first transferred to an adjoining chamber where the wafer is then passivated. The wafer is transferred to the adjoining chamber without exposing the wafer to the atmosphere outside the chambers.

Abstract: Connection ports for interconnecting functional modules in an integrated circuit are described. The connection ports provide enhanced functionality based around a common port primitive. This simplifies port design and selection and also allows a common packet protocol to be used for communication of packets across the packet router. In particular, there is improved functionality of target ports which allow out of order requests to be dealt with and out of order responses to be generated.

Abstract: A method is disclosed for processing the cleaved surface of a silicon-on-insulator structure. The silicon-on-insulator structures comprises a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The methods disclosed include an etching process to reduce the time and cost required to process the silicon-on-insulator structure to remove the surface damage and defects formed when a portion of the donor wafer is separated along a cleave plane from the silicon-on-insulator structure. The method includes, annealing the structure, etching the cleaved surface, and performing a non-contact smoothing process on the cleaved surface.

Abstract: A pipelined arbitration mechanism allows a routing control decision to be effected for a later packet while a current packet is being transferred. The later packet can be issued a fixed number of cycles after the current request. The mechanism has particular advantages when used with a plurality of functional modules connected to a packet router, whereby a single functional module can generate a current request relating to a current packet and a deferred arbitration request relating to a later packet to be issued a fixed number of cycles after the current request.

Abstract: A circuit for monitoring information put onto an interconnect by one or more modules, said circuit comprising circuitry for determining if the information on the interconnect matches one or more conditions; and circuitry for preventing a module from putting further information onto said interconnect if it is determined that information on the interconnect matches said one or more conditions.

Abstract: In a system comprising an interconnect and a plurality of modules connected to said interconnect for putting information onto the interconnect, a circuit comprising circuitry for receiving at least part of said of said information; circuitry for determining if said at least part of said information satisfies one or more conditions; and circuitry for performing one or more actions in response to the determination that at least part of the information satisfies one or more conditions.

Abstract: A data processing system having shared memory accessible through a transaction-based bus mechanism. A plurality of system components, including a central processor, are coupled to the bus mechanism. The bus mechanism includes a cache coherency transaction within its transaction set. The cache coherency transaction comprises a request issued by one of the system components that is recognized by a cache unit of the central processor as an explicit command to perform a cache coherency operation. The transaction further comprises a response issued by the central processor indicating status of the cache coherency operation.

Abstract: A data processing system having shared memory accessible through a transaction-based bus mechanism. A plurality of system components, including a central processor, are coupled to the bus mechanism. The bus mechanism includes a cache coherency transaction within its transaction set. The cache coherency transaction comprises a request issued by one of the system components that is recognized by a cache unit of the central processor as an explicit command to perform a cache coherency operation. The transaction further comprises a response issued by the central processor indicating status of the cache coherency operation.

Abstract: The implementation of transactions on an integrated circuit comprising a plurality of functional modules connected to a packet router is described. Each functional module generates request packets for implementing memory access operations, each request packet having an operation field comprising eight bits of which a packet type bit denotes the type of the packet, four operation family bit denote the function to be implemented by the packet and three operation qualifier bits act to qualify the function.