Abstract: Here, an apparatus is provided. The apparatus comprises a first supply rail, a second supply rail, a first ambipolar transistor (which is coupled to the first supply rail at its drain and which receives a reference voltage at its gate), a second ambipolar transistor (which is coupled to the first supply rail at its drain and which receives an input signal at its gate), a current source (which is coupled between the sources of the first and second ambipolar transistors and the second supply rail), and an output circuit (which is coupled to drain of the first ambipolar transistor). In operation, the output circuit provides an output signal having a frequency that is about twice the frequency of the input signal.

Abstract: An integrated circuit with a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. A method for forming a matching resistance heater. A method for operating an SOI integrated circuit containing a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair.

Abstract: Differential input pairs have been used in analog electronics with both CMOS and bipolar transistors for many years. Conventional designs for differential input pairs, though, may not be suitable for emerging technology transistors, such as graphene transistors, carbon nanotube (CNT) transistors, or other ambipolar transistors. Here, a differential input pair has been provided that uses ambipolar transistors, which accounts for the more unusual I-V (drain current to gate-source voltage) characteristics of ambipolar transistors.

Abstract: An integrated circuit includes common gate FinFET and split gate FinFET devices formed from different height fins at a semiconductor surface of a substrate. A patterned layer of gate electrode material formed over sides and unconnected over the tops of the taller fins defines respective gate electrodes for first and second paired transistors. The patterned layer of gate electrode material formed over the sides and connected over tops of the shorter fins defines common gate electrodes for transistors. In one embodiment, the common gate devices are used for cross-coupled inverters of a memory cell core storage element and the split gate devices are used for pass gates, with the gate electrodes coupled to wordlines and common source/drains coupled to bitline/complementary bitline and core element storage/complementary storage nodes.

Abstract: Current mirrors have been used in analog electronics with both CMOS and bipolar transistors for many years. Conventional current minor designs, though, may not be suitable for emerging technology transistors, such as graphene transistors, carbon nanotube (CNT) transistors, or other ambipolar transistors. Here, a current minor has been provided that uses ambipolar transistors, which accounts for the more unusual I-V (drain current to gate-source voltage) characteristics of ambipolar transistors.

Abstract: A ferrule for a conduit fitting includes in one embodiment a generally annular body comprising a cylindrical interior wall, a rearward portion with a frusto-conical recess that presents a camming surface, and a tapered outer surface. The tapered outer surface extends radially outwardly from a forward portion of the generally annular body towards the rearward portion, with the rearward portion further comprising an outer wall portion that tapers radially inwardly at an angle ? towards a back end of the annular body.

Abstract: Circuitry and methods for measuring capacitive mismatch with improved precision. The capacitors under measurement are connected in series in a voltage divider, with the node common to both capacitors connected to the gate of a source follower transistor. In one disclosed embodiment of the invention, a ramped voltage is applied to the drain of the source follower transistor simultaneously with the ramped voltage applied to the voltage divider; the slope of the ramped drain voltage is at the nominal slope of the voltage at the common node of the voltage divider. In another embodiment, a second transistor in saturation has its gate coupled to the source of the source follower device, and its source connected to the drain of the source follower device in series with a constant voltage drop. The drain-to-source voltage of the source follower device is thus held constant in each embodiment, improving precision of the measurement.

Abstract: One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with a second region of the semiconductor fin, where the fin capacitor has an approximately degenerate doping concentration in the second region. Other devices and methods are also disclosed.

Abstract: A turbofan engine comprising an annular inner wall surrounding tips of the fan blades, a layer of insulating material surrounding the inner wall, and an outer casing including an annular outer wall surrounding the insulating material and concentric to the inner wall and at least two annular rub elements extending radially inwardly from the outer wall through only part of a radial thickness of the layer of insulating material, at least two of the rub elements being in axial alignment with the blade tips at every point around a circumference of the fan, each rub element having a radially inner end spaced apart from the inner wall and made of a material harder than that of the blades, and a containment fabric layer wrapped around a support structure of the outer wall.

Abstract: The invention provides porous biomaterials and methods for forming porous biomaterials. The porous biomaterials of the invention comprise a biocompatible polymer scaffold defining an array of pores, wherein substantially all the pores have a similar diameter, wherein the mean diameter of the pores is between about 20 and about 90 micrometers, wherein substantially all the pores are each connected to at least 4 other pores, and wherein the diameter of substantially all the connections between the pores is between about 15% and about 40% of the mean diameter of the pores. The invention also provides implantable devices comprising a layer of a biomaterial, and methods for promoting angiogenesis in and around an implantable biomaterial.

Abstract: A method of manufacturing a semiconductor device having shallow trench isolation includes steps of forming a hard mask layer on the substrate surface, etching a trench through the hard mask, filling the trench with an isolation material, forming a recessed trench, and forming a serpentine gate structure to connect electronic sources and drains.

Abstract: A pair of split-gate fin field effect transistors (finFETs) in an IC, each containing a signal gate and a control gate, in which an adjustable voltage source, preferably in the form of a digital-to-analog-converter (DAC), is connected to the control gate of one of the finFETs, is disclosed. Threshold measurement circuits on the signal gates enable a threshold adjustment voltage from the adjustable voltage source to reduce the threshold mismatch between the finFETs. Adding a second DAC to the second finFET allows a simpler DAC design. Threshold correction may be performed during the operational life of the IC. Implementations in a differential input stage of an amplifier and in a current mirror circuit are described.

Abstract: Ferroelectric structures and methods of making the structures are presented. The ferroelectric structures can include an electrode in contact with a ferroelectric thin film. The contact can be arranged so that a portion of the atoms of the ferroelectric thin film are in contact with at least a portion of the atoms of the electrode. The electrode can be made of metal, a metal alloy, or a semiconducting material. A second electrode can be used and placed in contact with the ferroelectric thin film. Methods of making and using the ferroelectric structures are also presented.

Abstract: A body bias coordinator is provided for use with a transistor employing a body region. In one example, the body bias coordinator includes a control unit configured to control the transistor and make it operable to provide a virtual supply voltage from a source voltage during activation of the transistor. The body bias coordinator also includes a connection unit coupled to the control unit and configured to connect the body region to the virtual supply voltage during activation of the transistor. In an alternative embodiment, the connection unit is further configured to connect the body region to another voltage during non-activation of the transistor.

Abstract: The present invention provides a thermostatic bias controller for use with a memory array. The thermostatic bias controller includes a temperature sensing circuit configured to sense a temperature associated with the memory array. The thermostatic bias controller also includes a voltage control circuit coupled to the temperature sensing circuit and configured to provide a bias voltage to at least one back-gate of the memory array based on the temperature.

Abstract: A system and method for holographic lithography is disclosed, including interferometeric alignment of laser sources. This includes creation of the volumetric holographic pattern around wire and other planar and non-planar substrates. This template is further processed into devices for various applications including Photonic Crystals, Photonic Band Gaps, Photonic Band Gaps with selective defects, and Photonic Band Gap incandescent emitters.

Abstract: The present invention provides a body bias coordinator for use with a transistor employing a body region. In one embodiment, the body bias coordinator includes a control unit configured to control the transistor and make it operable to provide a virtual supply voltage from a source voltage during activation of the transistor. The body bias coordinator also includes a connection unit coupled to the control unit and configured to connect the body region to the virtual supply voltage during activation of the transistor. In an alternative embodiment, the connection unit is further configured to connect the body region to another voltage during non-activation of the transistor. These embodiments improve transistor active and passive performance, permit smaller transistor sizing and reduce leakage current.

Abstract: One embodiment relates to an on-chip power amplifier (PA) test circuit. In one embodiment, a PA test circuit comprises a controllable oscillator (CO) configured to generate a radio frequency (RF) signal, a parallel resonant circuit tuned to the radio frequency, a pre-power amplifier (PPA) coupled to the CO and the parallel resonant circuit, the PPA configured to amplify and drive the RF signal from an output of the PPA into a load. The test circuit may further comprise a first transmission gate configured to couple the RF signal from the CO to an input of the PPA. One testing methodology for a PA test circuit comprises stressing the PPA with an RF signal, measuring a characteristic of the PPA, determining stress degradation from the characteristic measurements, and repeating the stressing and characteristic measurements until a maximum stress degradation is achieved or a maximum stress has been applied.

Abstract: The invention provides porous biomaterials and methods for forming porous biomaterials. The porous biomaterials of the invention comprise a biocompatible polymer scaffold defining an array of pores, wherein substantially all the pores have a similar diameter, wherein the mean diameter of the pores is between about 20 and about 90 micrometers, wherein substantially all the pores are each connected to at least 4 other pores, and wherein the diameter of substantially all the connections between the pores is between about 15% and about 40% of the mean diameter of the pores. The invention also provides implantable devices comprising a layer of a biomaterial, and methods for promoting angiogenesis in and around an implantable biomaterial.

Abstract: A semiconductor device includes a fin-fuse and an SOI transistor. The SOI transistor is located on an SOI substrate and has a source region and a drain region. The fin-fuse is connected to one of the source/drain regions and has a fusible link located on the SOI substrate. The fusible link has a homogeneous dopant concentration.