Abstract: A high quality DAC is provided for a lower cost (including the layout size of the circuit on an audio chip) of high end DACs. The DAC includes a first circuit configured to remove even harmonics from a sigma delta circuit, and a second circuit configured to remove odd harmonics.

Abstract: The invention provides a method and apparatus for performing a voltage to current conversion. In particular, the invention provides a voltage to current converter configured to vary its transconductance (Gm). Such a converter is configured to receive a voltage input signal combined with a reference voltage signal to be converted to a current output. Optionally, the reference voltage signal may be provided by a parabolic impedance network that includes a bank of resistors and a plurality of corresponding current sources. Each current source corresponds to each node between two resistors, and may be varied in order to program changes in the comparator's Gm. Each resistor and corresponding current source is configured to create an individual reference voltage reference having a value that occurs in a parabolic manner in relation to other voltage references occurring across the impedance network. The converter further includes a plurality of comparators corresponding to the plurality of voltage reference signals.

Abstract: An improved segmented digital to analog converter is provided, configured with a novel method of compensating current flow in secondary or successive segmented elements. In operation, dual current devices initially load, then subsequently unload a cascade of resistor networks connected to the secondary or successive voltage segmenting elements, preventing the perturbation of precise operation of the primary or preceding elements. In contrast to conventional approaches, the improved converter obviates the need for a buffer or amplifier to isolate the secondary and successive voltage segmenting elements from the primary or preceding elements.

Abstract: A sigma delta circuit is provided having a sigma delta modulator configured to operate according to a first clock signal and a quantizer connected to the sigma delta modulator, where the quantizer is configured to operate according to a second clock signal. In operation, if a small amplitude signal is received by the sigma delta circuit, the circuit is configured to operate at a fixed output frequency. When a large amplitude signal is received, the circuit is configured to adjust to a different frequency to accommodate the larger signal. The second clock signal may be a variable clock signal, where the quantizer operates according to a variable clock signal in order to adjust to different input signals.

Abstract: The invention provides a frequency locked loop and related method that enables the conversion of a signal frequency with improved stability. A frequency locked loop embodying the invention includes an input for receiving an input signal and an output for outputting an output signal having a different frequency than the input. A frequency detector is configured to receive the first factored input from the primary channel and the second factored input from the secondary channel, to calculate the difference between the first factored input and the second factored input and to produce an output based on the difference between the two factored inputs. A voltage controlled oscillator is configured to receive the output from the frequency detector, and to produce an output signal. The voltage controlled oscillator ultimately sets the output frequency based on the output of frequency detector.

Abstract: A circuit and related method for digital volume control are provided, where the circuit includes a digital filter configured to process samples of an input stream in a manner that processes a previous input sample during a time interval before a subsequent input sample, and outputs a series of exponentially decaying waveforms. The result is an exponential response to a volume change made by a user, where the change feels more pleasant and natural than a conventional linear response.

Abstract: A high quality DAC is provided for a lower cost (including the layout size of the circuit on an audio chip) of high end DACs. The DAC includes a first circuit configured to remove even harmonics from a sigma delta circuit, and a second circuit configured to remove odd harmonics.

Abstract: A device is provided having at least two capacitive elements configured to retain a charge, and an interconnection of active devices between the capacitive elements. The active devices are configured to operate upon a transient charge flow as a current when in operation. The charge flow is partitioned into at least two capacitors according to the input voltage difference acting as a controlling parameter.

Abstract: A circuit is provided having a secondary semi-analog FIR filter connected to a primary filter via a coefficient to reduce the size of the sizes of the resistors used in the primary filter. The coefficient may be one or more intermediate resistors connected between separate resistor/voltage driver banks that make up the FIR filter. The result is a circuit that takes up less chip space required to accommodate the required resistance for a digital to analog converter (DAC). The invention configures the resistor structure to produce the same output result as a conventional circuit, but with smaller resistor values that take up less surface area on the chip.

Abstract: The invention provides a frequency locked loop and related method that enables the conversion of a signal frequency with improved stability. X frequency locked loop embodying the invention includes an input for receiving an input signal and an output for outputting an output signal having a different frequency than the input. A frequency detector is configured to receive the first factored input from the primary channel and the second factored input from the secondary channel, to calculate the difference between the first factored input and the second factored input and to produce an output based on the difference between the two factored inputs. A voltage controlled oscillator is configured to receive the output from the frequency detector and to produce an output signal. The voltage controlled oscillator ultimately sets the output frequency based on the output of frequency detector.

Abstract: A circuit is provided having a secondary semi-analog FIR filter connected to a primary filter via a coefficient to reduce the size of the sizes of the resistors used in the primary filter. The coefficient may be one or more intermediate resistors connected between separate resistor/voltage driver banks that make up the FIR filter. The result is a circuit that takes up less chip space required to accommodate the required resistance for a digital to analog converter (DAC). The invention configures the resistor structure to produce the same output result as a conventional circuit, but with smaller resistor values that take up less surface area on the chip.

Abstract: The invention provides a method and apparatus for performing a voltage to current conversion. In particular, the invention provides a voltage to current converter configured to vary its transconductance (Gm). Such a converter is configured to receive a voltage input signal combined with a reference voltage signal to be converted to a current output. Optionally, the reference voltage signal may be provided by a parabolic impedance network that includes a bank of resistors and a plurality of corresponding current sources. Each current source corresponds to each node between two resistors, and may be varied in order to program changes in the comparator's Gm. Each resistor and corresponding current source is configured to create an individual reference voltage reference having a value that occurs in a parabolic manner in relation to other voltage references occurring across the impedance network. The converter further includes a plurality of comparators corresponding to the plurality of voltage reference signals.

Abstract: An electronic device is provided such as an amplifier, for example, having improved gain and transconductance and low output impedance. The device includes a primary amplifier configured to carry an operating load. The primary amplifier includes an input for receiving an input signal, and an output for outputting an output signal, and operates having a variable output, as it carries an operational load. The device further includes a secondary amplifier configured to operate at a fixed operating condition, not burdened by carrying an operational load, and includes a secondary input configured to receive the input signal, wherein the secondary amplifier is configured to define the input voltage. The device is configured to detect a difference in operating current between the primary and secondary amplifiers, and to compensate for any operational load that may be applied to the primary amplifier during operation.

Abstract: A high quality DAC is provided for a lower cost (including the layout size of the circuit on an audio chip) of high end DACs. The DAC includes a first circuit configured to remove even harmonics from a sigma delta circuit, and a second circuit configured to remove odd harmonics.

Abstract: An improved segmented analog to digital converter is provided, configured with a novel method of compensating current flow in secondary or successive segmented elements. In operation, dual current devices initially load, then subsequently unload a cascade of resistor networks connected to the secondary or successive voltage segmenting elements, preventing the perturbation of precise operation of the primary or preceding elements. In contrast to conventional approaches, the improved converter obviates the need for a buffer or amplifier to isolate the secondary and successive voltage segmenting elements from the primary or preceding elements.

Abstract: A signal processor has a plurality of channels, each channel configured to receive an input signal stream, to reduce the signal to a direct current signal and to process the signal according to the stream signal. Each channel also has a plurality of low pass filters configured to filter in-phase and quadrature-phase modulator outputs with a first low pass filter and to filter a reference quadrature signals, and a gain control configured to re-modulate gain adjusted output signals with the filtered quadrature signals. The processor further includes an inverter to invert the in-phase filtered reference signal and means to multiply the quadrature gain adjusted output signal.

Abstract: A system and method are provided for compensating for output error in a sigma delta circuit. The system includes an input for receiving an input signal and an output configured to output a output signal. The system further includes a summation component configured to add a first error voltage value, which is derived from an output signal, to an incoming input signal, and a subtraction component configured to subtract a second error voltage value, where the second error voltage value is derived from the adding of a first error voltage value to an incoming input signal.

Abstract: A differential input flash analog-to-digital converter in which an array of comparators is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signal across an impedance network. Preferably, the comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, and the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Even more preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range of the converter. The flash converter according to the invention provides increased gain from input without accumulation of comparator input currents and without sacrificing the number of actual comparisons of reference signals.

Abstract: A sigma delta circuit is provided having a sigma delta modulator configured to operate according to a first clock signal and a quantizer connected to the sigma delta modulator, where the quantizer is configured to operate according to a second clock signal. In operation, if a small amplitude signal is received by the sigma delta circuit, the circuit is configured to operate at a fixed output frequency. When a large amplitude signal is received, the circuit is configured to adjust to a different frequency to accommodate the larger signal. The second clock signal may be a variable clock signal, where the quantizer operates according to a variable clock signal in order to adjust to different input signals.

Abstract: An electronic device is provided such as an amplifier, for example, having improved gain and transconductance and low output impedance. The device includes a primary amplifier configured to carry an operating load. The primary amplifier includes an input for receiving an input signal, and an output for outputting an output signal, and operates having a variable output, as it carries an operational load. The device further includes a secondary amplifier configured to operate at a fixed operating condition, not burdened by carrying an operational load, and includes a secondary input configured to receive the input signal, wherein the secondary amplifier is configured to define the input voltage. The device is configured to detect a difference in operating current between the primary and secondary. amplifiers, and to compensate for any operational load that may be applied to the primary amplifier during operation.