Abstract: A method for processing a substrate includes performing a cyclic plasma process including a plurality of cycles, each cycle of the plurality of cycles including purging a plasma processing chamber including the substrate with a first deposition gas including carbon. The substrate includes a first layer including silicon and a second layer including a metal oxide. The method further includes exposing the substrate to a first plasma generated from the first deposition gas to selectively deposit a first polymeric film over the first layer relative to the second layer; purging the plasma processing chamber with an etch gas including fluorine; and exposing the substrate to a second plasma generated from the etch gas to etch the second layer.

Abstract: A method of processing a substrate that includes: flowing nitrogen-containing (N-containing) gas, dioxygen (O2), a noble gas, and a fluorocarbon into the plasma processing chamber, the plasma processing chamber configured to hold a substrate including a dielectric layer as etch target and a patterned hardmask over the target layer; while flowing the gases, generating a fluorine-rich and nitrogen-deficient plasma in the plasma processing chamber, fluorine-rich and nitrogen-deficient plasma being made of more number of fluorine species than nitrogen species; and forming a high aspect ratio feature by exposing the substrate to the fluorine-rich and nitrogen-deficient plasma to etch a recess in the dielectric layer.

Abstract: A method of processing a substrate that includes: loading the substrate into a plasma etch chamber, the substrate including a patterned hard mask layer and an underlying layer, the plasma etch chamber including: a chamber part having a surface including a refractory metal; and a first electrode; flowing a process gas into the plasma etch chamber; while flowing the process gas, applying a source power to the first electrode of the plasma etch chamber to generate a plasma in the plasma etch chamber; exposing the surface of the chamber part to the plasma to sputter the refractory metal from the surface of the chamber part; and exposing the substrate to the plasma to deposit the refractory metal onto a portion of the patterned hard mask layer and etch the underlying layer selectively to the patterned hard mask layer.

Abstract: Various embodiments of stacked structures, process steps and methods are provided herein for etching high aspect ratio features (e.g., contact holes, vias, trenches, etc.) within a stacked structure comprising a hard mask layer, which is formed above and in contact with one or more underlying layers. At least one etch stop layer (ESL) is provided within the hard mask layer to divide the hard mask layer into two or more distinct portions. When the stacked structure is subsequently etched to form high aspect ratio features within the hard mask layer, such as contact holes or vias that extend through the hard mask layer, the ESL(s) included within the hard mask layer improve etch rate and critical dimension (CD) uniformity of the features etched within the hard mask layer.

Abstract: A method of fabricating an amorphous carbon layer (ACL) mask includes forming an ACL on an underlying layer. The ACL includes a soft ACL portion that has a first hardness and a hard ACL portion that has a second hardness. The soft ACL portion underlies the hard ACL portion. The second hardness is greater than the first hardness. The method further includes forming a patterned layer over the ACL and forming an ACL mask by etching through both the soft ACL portion and the hard ACL portion of the ACL to expose the underlying layer using the patterned layer as an etch mask. Forming the ACL may include depositing one or both of the soft ACL portion and the hard ACL portion. Processing conditions may also be varied while forming the ACL to create a hardness gradient that transitions from softer to harder.

Abstract: A semiconductor device structure includes a dielectric layer formed on a silicon substrate, an amorphous carbon layer (ACL) formed on the dielectric layer, and a charge dissipation layer formed between the ACL and the dielectric layer. The charge dissipation layer is formed from a material having a resistivity lower than the resistivity of the ACL Methodologies to fabricate the semiconductor device structure are also disclosed and include forming the dielectric layer on the silicon substrate, forming the charge dissipation layer on the dielectric layer, and forming the ACL on the charge dissipation layer. Alternative semiconductor device structures and fabrication methodologies are also disclosed.

Abstract: Improved process flows and methods are provided herein for forming a passivation layer on sidewall surfaces of openings formed in an amorphous carbon layer (ACL) to avoid bowing during an ACL etch process. More specifically, improved process flows and methods are provided to form a silicon-containing passivation layer on sidewall surfaces of the openings created within the ACL without utilizing atomic layer deposition (ALD) techniques or converting the silicon-containing passivation layer to an oxide or a nitride. As such, the improved process flows and methods disclosed herein may be used to protect the sidewall surfaces of the ACL and prevent bowing during the ACL etch process, while also reducing processing time and improving throughput.

Abstract: A method of processing a substrate that includes: flowing a first unsaturated fluorocarbon, a saturated fluorocarbon, a first noble gas, and dioxygen into a plasma chamber; while flowing these gases, generating a plasma in the plasma chamber; and patterning, with the plasma, a material layer on the substrate.

Abstract: Methods and improved process flows are provided herein for forming self-aligned contacts using spin-on silicon carbide (SiC). More specifically, the disclosed methods and process flows form self-aligned contacts by using spin-on SiC as a cap layer for at least one other structure, instead of depositing a SiC layer via plasma vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The other structure may be a source and drain contact made through the use of a trench conductor. By utilizing spin-on SiC as a cap layer material, the disclosed methods and process flows avoid problems that typically occur when SiC is deposited, for example by CVD, and subsequently planarized. As such, the disclosed methods and process flows improve upon conventional methods and process flows for forming self-aligned contacts by reducing defectivity and improving yield.

Abstract: A method for processing a substrate includes performing a cyclic process including a plurality of cycles, where the cyclic process includes: forming, in a plasma processing chamber, a passivation layer over sidewalls of a recess in a carbon-containing layer, by exposing the substrate to a first gas including boron, silicon, or aluminum, the carbon-containing layer being disposed over a substrate, purging the plasma processing chamber with a second gas including a hydrogen-containing gas, an oxygen-containing gas, or molecular nitrogen, and exposing the substrate to a plasma generated from the second gas, where each cycle of the plurality of cycles extends the recess vertically into the carbon-containing layer.

Abstract: In one embodiment, a method includes providing a substrate comprising a source/drain contact region and a dummy gate, forming a first etch stop layer aligned to the source/drain contact region, where the first etch stop layer does not cover the dummy gate. The method may include forming a second etch stop layer over the first etch stop layer, the second etch stop layer covering the first etch stop layer and the dummy gate. The method may include converting the dummy gate to a metal gate. The method may include removing the second etch stop layer using a plasma etching process. The method may include removing the first etch stop layer.

Abstract: A method for processing a substrate includes performing a cyclic plasma process including a plurality of cycles, each cycle of the plurality of cycles including purging a plasma processing chamber including the substrate with a first deposition gas including carbon. The substrate includes a first layer including silicon and a second layer including a metal oxide. The method further includes exposing the substrate to a first plasma generated from the first deposition gas to selectively deposit a first polymeric film over the first layer relative to the second layer; purging the plasma processing chamber with an etch gas including fluorine; and exposing the substrate to a second plasma generated from the etch gas to etch the second layer.

Abstract: A method which includes providing a substrate having a source/drain region and an etch stop layer on the source/drain region. A plasma etching process is performed using an etching gas that removes the etch stop layer and forms a sacrificial oxide capping layer on the source/drain region. The sacrificial oxide capping layer is then from the source/drain region.

Abstract: A method for processing a substrate includes performing a cyclic process including a plurality of cycles, where the cyclic process includes: forming, in a plasma processing chamber, a passivation layer over sidewalls of a recess in a carbon-containing layer, by exposing the substrate to a first gas including boron, silicon, or aluminum, the carbon-containing layer being disposed over a substrate, purging the plasma processing chamber with a second gas including a hydrogen-containing gas, an oxygen-containing gas, or molecular nitrogen, and exposing the substrate to a plasma generated from the second gas, where each cycle of the plurality of cycles extends the recess vertically into the carbon-containing layer.

Abstract: Systems and methods are provided herein for etch features on a substrate, while maintaining a near-unity critical dimension (CD) shrink ratio. The features etched may include, but are not limited to contacts, vias, etc. More specifically, the techniques described herein use a pulsed plasma to control the polymer build-up ratio between the major CD and minor CD of the feature, and thus, control the CD shrink ratio when etching features having substantially different major and minor dimensions. The CD shrink ratio is controlled by selecting or adjusting one or more operational parameters (e.g., duty cycle, RF power, etch chemistry, etc.) of the plasma etch process(es) to control the amount of polymer build-up at the major and minor dimensions of the feature.

Abstract: A method for manufacturing a FET semiconductor structure includes providing a substrate comprising at least one source/drain contact of at least one FET, the at least one source/drain contact formed adjacent to a dummy gate of the at least one FET. A TiSi2 film with C54 structure is selectively deposited directly on and fully covering the at least one source/drain contact relative to a vertical sidewall of a gate spacer between the at least one source/drain contact and the dummy gate. The dummy gate is replaced with a replacement metal gate.

Abstract: A method includes providing a substrate including metal gate stacks and source/drain contact regions in alternating arrangement along a surface of the substrate with a dielectric spacer separating each source/drain contact region from adjacent metal gate stacks. Each source/drain region is recessed within an opening between adjacent metal gate stacks such that source/drain contact regions provide a bottom of the recess and dielectric spacers provide sidewalls. The etch stop layer is formed on the substrate such that it conformally covers the metal gate stacks, the sidewalls and the bottom of each recess, and a sacrificial layer is formed over each of the metal gate stacks and on at least a portion of each sidewall. The etch stop layer is removed from the bottom of each recess to expose the source/drain contact, and the sacrificial layer is then removed from the metal gate stacks and the sidewalls of each recess.

Abstract: Methods and improved process flows are provided herein for forming self-aligned contacts using spin-on silicon carbide (SiC). More specifically, the disclosed methods and process flows form self-aligned contacts by using spin-on SiC as a cap layer for at least one other structure, instead of depositing a SiC layer via plasma vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The other structure may be a source and drain contact made through the use of a trench conductor. By utilizing spin-on SiC as a cap layer material, the disclosed methods and process flows avoid problems that typically occur when SiC is deposited, for example by CVD, and subsequently planarized. As such, the disclosed methods and process flows improve upon conventional methods and process flows for forming self-aligned contacts by reducing defectivity and improving yield.

Abstract: Methods and improved process flows are provided herein for forming self-aligned contacts using spin-on silicon carbide (SiC). More specifically, the disclosed methods and process flows form self-aligned contacts by using spin-on SiC as a cap layer for at least one other structure, instead of depositing a SiC layer via plasma vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The other structure may be a source and drain contact made through the use of a trench conductor. By utilizing spin-on SiC as a cap layer material, the disclosed methods and process flows avoid problems that typically occur when SiC is deposited, for example by CVD, and subsequently planarized. As such, the disclosed methods and process flows improve upon conventional methods and process flows for forming self-aligned contacts by reducing defectivity and improving yield.

Abstract: Improved process flows and methods are provided herein for fabricating a transistor on a substrate. In the disclosed process flows and methods, a contact etch stop layer (CESL) is conformally deposited directly onto a plurality of transistor structures, and a sacrificial layer is conformally deposited directly onto the CESL to protect the CESL from oxidation and thinning during subsequent processing step(s). The sacrificial layer improves the etch stop capability of the CESL during a subsequently performed oxide etch process. By providing a CESL with improved etch stop capability, the disclosed process flows and methods provide a controlled CESL etch process, which reduces or avoids damage to underlying transistor structures.