Patents by Inventor Andrew P. Edwards
Andrew P. Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250006784Abstract: A method for manufacturing a semiconductor device includes: providing a semiconductor substrate; epitaxially growing a first semiconductor layer coupled to the semiconductor substrate; epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer comprises a contact region and a terminal region surrounding the contact region; forming a mask layer on the second semiconductor layer, wherein the mask layer is patterned with a tapered region aligned with the terminal region of the second semiconductor layer; implanting ions into the terminal region of the second semiconductor layer using the mask layer to form a tapered junction termination element in the terminal region of the second semiconductor layer; and forming a contact structure in the contact region of the second semiconductor layer.Type: ApplicationFiled: September 16, 2024Publication date: January 2, 2025Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Subhash Srinivas PIDAPARTHI, Andrew P. EDWARDS, Clifford DROWLEY, Kedar PATEL
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Patent number: 12155204Abstract: A method of clamping a voltage includes providing a fin-based field effect transistor (FinFET) device. The FinFET device includes an array of FinFETs. Each FinFET includes a source contact electrically coupled to a fin and a gate contact. The method also includes applying the voltage to the source contact and applying a second voltage to the gate contact. The voltage is greater than the second voltage. The method further includes increasing the voltage to a threshold voltage and conducting current from the source contact to the gate contact in response to the voltage reaching the threshold voltage.Type: GrantFiled: April 20, 2023Date of Patent: November 26, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Andrew J. Walker, Clifford Drowley, Subhash Srinivas Pidaparthi, Andrew P. Edwards, Shahin Sharifzadeh, Joseph Tandingan
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Patent number: 12136645Abstract: A semiconductor device includes an active device region and a plurality of guard rings arranged in a first concentric pattern surrounding the active device region. The semiconductor device also includes a plurality of junctions arranged in a second concentric pattern surrounding the active device region. At least one of the plurality of junctions is arranged between two adjacent guard rings of the plurality of guard rings, and the plurality of junctions have a different resistivity than the plurality of guard rings. The semiconductor device further includes a plurality of coupling paths. At least one of the plurality of coupling paths is arranged to connect two adjacent guard rings of the plurality of guard rings.Type: GrantFiled: January 25, 2022Date of Patent: November 5, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Clifford Drowley, Andrew P. Edwards, Hao Cui, Subhash Srinivas Pidaparthi
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Patent number: 12125914Abstract: A method of fabricating a vertical fin-based field effect transistor (FET) includes providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type, epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer, and epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer. The method also includes forming a metal compound layer on the second semiconductor layer, forming a patterned hard mask layer on the metal compound layer, and etching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench.Type: GrantFiled: June 23, 2023Date of Patent: October 22, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Clifford Drowley, Ray Milano, Subhash Srinivas Pidaparthi, Andrew P. Edwards, Hao Cui, Shahin Sharifzadeh
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Patent number: 12113101Abstract: A method for manufacturing a semiconductor device includes: providing a semiconductor substrate; epitaxially growing a first semiconductor layer coupled to the semiconductor substrate; epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer comprises a contact region and a terminal region surrounding the contact region; forming a mask layer on the second semiconductor layer, wherein the mask layer is patterned with a tapered region aligned with the terminal region of the second semiconductor layer; implanting ions into the terminal region of the second semiconductor layer using the mask layer to form a tapered junction termination element in the terminal region of the second semiconductor layer; and forming a contact structure in the contact region of the second semiconductor layer.Type: GrantFiled: July 7, 2021Date of Patent: October 8, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Subhash Srinivas Pidaparthi, Andrew P. Edwards, Clifford Drowley, Kedar Patel
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Publication number: 20240274545Abstract: A method of forming alignment marks includes providing a III-V compound substrate having a device region and an alignment mark region, forming a hardmask layer having a first set of openings on the alignment mark region exposing a first surface portion of the III-V compound substrate and a second set of openings on the device region exposing a second surface portion of the III-V compound substrate, etching the exposed surface of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches, and epitaxially regrowing a semiconductor layer in the trenches to form the alignment marks extending to a predetermined height over the processing surface of the III-V compound substrate.Type: ApplicationFiled: March 12, 2024Publication date: August 15, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Clifford Drowley, Ray Milano, Robert Routh, Subhash Srinivas Pidaparthi, Andrew P. Edwards
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Publication number: 20240274725Abstract: Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.Type: ApplicationFiled: March 8, 2024Publication date: August 15, 2024Applicant: Semiconductor Components Industries, LLCInventors: Clifford Drowley, Andrew P. Edwards, Subhash Srinivas Pidaparthi, Ray Milano
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Publication number: 20240274602Abstract: A method for manufacturing a vertical FET device includes providing a semiconductor substrate structure including a semiconductor substrate and a first semiconductor layer coupled to the semiconductor substrate. The first semiconductor layer is characterized by a first conductivity type. The method also includes forming a plurality of semiconductor fins coupled to the first semiconductor layer. Each of the plurality of semiconductor fins is separated by one of a plurality of recess regions. The method further includes epitaxially regrowing a semiconductor gate layer including a surface region in the plurality of recess regions. The method also includes forming an isolation region within the surface region of the semiconductor gate layer. The isolation region surrounds each of the plurality of semiconductor fins. The method includes forming a source contact structure coupled to each of the plurality of semiconductor fins and forming a gate contact structure coupled to the semiconductor gate layer.Type: ApplicationFiled: April 22, 2024Publication date: August 15, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Clifford DROWLEY, Hao CUI, Andrew P. EDWARDS, Subhash Srinivas PIDAPARTHI
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Publication number: 20240258408Abstract: A method of fabricating a semiconductor device includes providing a substrate structure comprising a semiconductor substrate of a first conductivity type, a drift layer on the semiconductor substrate, and a fin array on the drift layer and surrounded by a recess region. The fin array comprises a first row of fins and a second row of fins parallel to each other and separated from each other by a space. The first row of fins comprises a plurality of first elongated fins extending parallel to each other in a first direction. The second row of fins comprises a plurality of second elongated fins extending parallel to each other in a second direction parallel to the first direction. The method also includes epitaxially regrowing a gate layer surrounding the first and second row of fins on the drift layer and filling the recess region.Type: ApplicationFiled: February 26, 2024Publication date: August 1, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Clifford Drowley, Ray Milano, Subhash Srinivas Pidaparthi, Andrew P. Edwards
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Publication number: 20240242969Abstract: A method of manufacturing a vertical FET device includes providing a semiconductor substrate structure including a marker layer; forming a hardmask layer coupled to the semiconductor substrate structure, wherein the hardmask layer comprises a set of openings operable to expose an upper surface portion of the semiconductor substrate structure; etching the upper surface portion of the semiconductor substrate structure to form a plurality of fins; etching at least a portion of the marker layer; detecting the etching of the at least a portion of the marker layer; epitaxially growing a semiconductor layer in recess regions disposed between adjacent fins of the plurality of fins; forming a source metal layer on each of the plurality of fins; and forming a gate metal layer coupled to the semiconductor layer.Type: ApplicationFiled: March 28, 2024Publication date: July 18, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Wayne CHEN, Andrew P. EDWARDS, Clifford DROWLEY, Subhash Srinivas PIDAPARTHI
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Patent number: 11996407Abstract: A method for manufacturing a vertical FET device includes providing a semiconductor substrate structure including a semiconductor substrate and a first semiconductor layer coupled to the semiconductor substrate. The first semiconductor layer is characterized by a first conductivity type. The method also includes forming a plurality of semiconductor fins coupled to the first semiconductor layer. Each of the plurality of semiconductor fins is separated by one of a plurality of recess regions. The method further includes epitaxially regrowing a semiconductor gate layer including a surface region in the plurality of recess regions. The method also includes forming an isolation region within the surface region of the semiconductor gate layer. The isolation region surrounds each of the plurality of semiconductor fins. The method includes forming a source contact structure coupled to each of the plurality of semiconductor fins and forming a gate contact structure coupled to the semiconductor gate layer.Type: GrantFiled: July 12, 2021Date of Patent: May 28, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Clifford Drowley, Hao Cui, Andrew P. Edwards, Subhash Srinivas Pidaparthi
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Publication number: 20240120417Abstract: A gallium nitride (GaN) power device includes a GaN substrate structure having a first surface and a second surface, a metallic layer coupled to the second surface of the GaN substrate structure, and an active region including an array of vertical fin-based field effect transistors (FinFETs) coupled to the GaN substrate structure. The GaN power device also includes an edge termination structure circumscribing the active region and a seal ring structure circumscribing the edge termination structure and comprising a seal ring metal pad operable to conduct charge from the edge termination structure to the metallic layer.Type: ApplicationFiled: April 20, 2023Publication date: April 11, 2024Applicant: Nexgen Power Systems, Inc.Inventors: Kyoung Wook Seok, Clifford Drowley, Andrew J. Walker, Andrew P. Edwards
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Patent number: 11948801Abstract: A method of manufacturing a vertical FET device includes providing a semiconductor substrate structure including a marker layer; forming a hardmask layer coupled to the semiconductor substrate structure, wherein the hardmask layer comprises a set of openings operable to expose an upper surface portion of the semiconductor substrate structure; etching the upper surface portion of the semiconductor substrate structure to form a plurality of fins; etching at least a portion of the marker layer; detecting the etching of the at least a portion of the marker layer; epitaxially growing a semiconductor layer in recess regions disposed between adjacent fins of the plurality of fins; forming a source metal layer on each of the plurality of fins; and forming a gate metal layer coupled to the semiconductor layer.Type: GrantFiled: June 23, 2021Date of Patent: April 2, 2024Assignee: Nexgen Power Systems, Inc.Inventors: Wayne Chen, Andrew P. Edwards, Clifford Drowley, Subhash Srinivas Pidaparthi
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Patent number: 11935838Abstract: A method of forming alignment marks includes providing a III-V compound substrate having a device region and an alignment mark region, forming a hardmask layer having a first set of openings on the alignment mark region exposing a first surface portion of the III-V compound substrate and a second set of openings on the device region exposing a second surface portion of the III-V compound substrate, etching the exposed surface of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches, and epitaxially regrowing a semiconductor layer in the trenches to form the alignment marks extending to a predetermined height over the processing surface of the III-V compound substrate.Type: GrantFiled: March 29, 2022Date of Patent: March 19, 2024Assignee: Nexgen Power Systems, Inc.Inventors: Clifford Drowley, Ray Milano, Robert Routh, Subhash Srinivas Pidaparthi, Andrew P. Edwards
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Patent number: 11929440Abstract: Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.Type: GrantFiled: March 9, 2023Date of Patent: March 12, 2024Assignee: Nexgen Power Systems, Inc.Inventors: Clifford Drowley, Andrew P. Edwards, Subhash Srinivas Pidaparthi, Ray Milano
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Patent number: 11916134Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a drift layer of the first conductivity type coupled to the semiconductor substrate, a fin array having a first row of fins and a second row of fins on the drift layer, and a space between the first row of fins and the second row of fins. The first row of fins includes a plurality of first elongated fins arranged in parallel to each other along a first row direction and separated by a first distance, and the second row of fins includes a plurality of second elongated fins arranged in parallel to each other along a second row direction and separated by a second distance.Type: GrantFiled: December 28, 2020Date of Patent: February 27, 2024Assignee: NEXGEN POWER SYSTEMS, INC.Inventors: Clifford Drowley, Ray Milano, Subhash Srinivas Pidaparthi, Andrew P. Edwards
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Publication number: 20230420547Abstract: A transistor includes a III-nitride substrate, a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type, and a plurality of III-nitride fins on the first III-nitride layer, wherein each of the plurality of III-nitride fins is separated by one of a plurality of first recess regions and characterized by a fin surface, wherein the plurality of III-nitride fins are characterized by the first conductivity type. The transistor also includes a III-nitride gate layer having a second conductivity type opposite to the first conductivity type in the plurality of first recess regions, wherein a surface of the III-nitride gate layer is substantially coplanar with the fin surface, and a regrown III-nitride source contact portion coupled to each of the plurality of III-nitride fins, wherein the regrown III-nitride source contact portion is characterized by the first conductivity type.Type: ApplicationFiled: June 23, 2023Publication date: December 28, 2023Applicant: NEXGEN POWER SYSTEMS, INC.Inventors: Clifford Drowley, Andrew P. Edwards, Subhash Srinivas Pidaparthi, Shahin Sharifzadeh
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Publication number: 20230411525Abstract: A method of fabricating a vertical fin-based field effect transistor (FET) includes providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type, epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer, and epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer. The method also includes forming a metal compound layer on the second semiconductor layer, forming a patterned hard mask layer on the metal compound layer, and etching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench.Type: ApplicationFiled: June 23, 2023Publication date: December 21, 2023Applicant: Nexgen Power Systems, Inc.Inventors: Clifford Drowley, Ray Milano, Subhash Srinivas Pidaparthi, Andrew P. Edwards, Hao Cui, Shahin Sharifzadeh
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Publication number: 20230378348Abstract: A vertical, FinFET device includes an array of FinFETs comprising a plurality of rows and columns of fins. Each of the fins has a fin length and a fin width, a first fin tip, a second fin tip, and a central region disposed between the first fin tip of a first row of the plurality of rows and the second fin tip of a second row of the plurality of rows. The central region is characterized by an electrical conductivity. The FinFET device also includes a neutralized region including the first fin tip, a region between the first row of the plurality of rows and the second row of the plurality of rows, and the second fin tip. The neutralized region is characterized by a second electrical conductivity less than the electrical conductivity of the central region. The FinFET device further includes an electrical conductor disposed over the neutralized region.Type: ApplicationFiled: April 20, 2023Publication date: November 23, 2023Applicant: Nexgen Power Systems, Inc.Inventors: Clifford Drowley, Andrew J. Walker, Andrew P. Edwards, Subhash Srinivas Pidaparthi, Thomas E. Kopley
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Publication number: 20230378750Abstract: A method of clamping a voltage includes providing a fin-based field effect transistor (FinFET) device. The FinFET device includes an array of FinFETs. Each FinFET includes a source contact electrically coupled to a fin and a gate contact. The method also includes applying the voltage to the source contact and applying a second voltage to the gate contact. The voltage is greater than the second voltage. The method further includes increasing the voltage to a threshold voltage and conducting current from the source contact to the gate contact in response to the voltage reaching the threshold voltage.Type: ApplicationFiled: April 20, 2023Publication date: November 23, 2023Applicant: Nexgen Power Systems, Inc.Inventors: Andrew J. Walker, Clifford Drowley, Subhash Srinivas Pidaparthi, Andrew P. Edwards, Shahin Sharifzadeh, Joseph Tandingan