Patents by Inventor Andrew P. Edwards
Andrew P. Edwards has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220310843Abstract: A method of fabricating a vertical fin-based field effect transistor (FET) includes providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type, epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer, and epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer. The method also includes forming a metal compound layer on the second semiconductor layer, forming a patterned hard mask layer on the metal compound layer, and etching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench.Type: ApplicationFiled: April 12, 2022Publication date: September 29, 2022Applicant: NEXGEN POWER SYSTEMS, INC.Inventors: Clifford Drowley, Ray Milano, Subhash Srinivas Pidaparthi, Andrew P. Edwards, Hao Cui, Shahin Sharifzadeh
-
Publication number: 20220293530Abstract: A method of forming alignment marks includes providing a III-V compound substrate having a device region and an alignment mark region, forming a hardmask layer having a first set of openings on the alignment mark region exposing a first surface portion of the III-V compound substrate and a second set of openings on the device region exposing a second surface portion of the III-V compound substrate, etching the exposed surface of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches, and epitaxially regrowing a semiconductor layer in the trenches to form the alignment marks extending to a predetermined height over the processing surface of the III-V compound substrate.Type: ApplicationFiled: March 29, 2022Publication date: September 15, 2022Applicant: NexGen Power Systems, Inc.Inventors: Clifford Drowley, Ray Milano, Robert Routh, Subhash Srinivas Pidaparthi, Andrew P. Edwards
-
Publication number: 20220254918Abstract: A vertical FET device includes a semiconductor structure comprising a semiconductor substrate, a first semiconductor layer coupled to the semiconductor substrate, and a second semiconductor layer coupled to the first semiconductor layer. The vertical FET device also includes a plurality of fins. Adjacent fins of the plurality of fins are separated by a trench extending into the second semiconductor layer and each of the plurality of fins includes a channel region disposed in the second semiconductor layer. The vertical FET also includes a gate region extending into a sidewall portion of the channel region of each of the plurality of fins, a source metal structure coupled to the second semiconductor layer, a gate metal structure coupled to the gate region, and a drain contact coupled to the semiconductor substrate.Type: ApplicationFiled: February 8, 2022Publication date: August 11, 2022Applicant: NexGen Power Systems, Inc.Inventors: Clifford Drowley, Hao Cui, Andrew P. Edwards, Subhash Srinivas Pidaparthi
-
Publication number: 20220238643Abstract: A semiconductor device includes an active device region and a plurality of guard rings arranged in a first concentric pattern surrounding the active device region. The semiconductor device also includes a plurality of junctions arranged in a second concentric pattern surrounding the active device region. At least one of the plurality of junctions is arranged between two adjacent guard rings of the plurality of guard rings, and the plurality of junctions have a different resistivity than the plurality of guard rings. The semiconductor device further includes a plurality of coupling paths. At least one of the plurality of coupling paths is arranged to connect two adjacent guard rings of the plurality of guard rings.Type: ApplicationFiled: January 25, 2022Publication date: July 28, 2022Applicant: NexGen Power Systems, Inc.Inventors: Clifford Drowley, Andrew P. Edwards, Hao Cui, Subhash Srinivas Pidaparthi
-
Patent number: 11335810Abstract: A transistor includes a substrate having a first surface and a second surface opposite the first surface, a drift region having a doped region on the first surface of the substrate and a graded doping region on the doped region, a semiconductor fin protruding from the graded doping region and comprising a metal compound layer at an upper portion of the semiconductor fin, a source metal contact on the metal compound layer, a gate layer having a bottom portion directly contacting the graded doping region; and a drain metal contact on the second surface of the substrate.Type: GrantFiled: July 15, 2020Date of Patent: May 17, 2022Assignee: NEXGEN POWER SYSTEMS, INC.Inventors: Clifford Drowley, Ray Milano, Subhash Srinivas Pidaparthi, Andrew P. Edwards, Hao Cui, Shahin Sharifzadeh
-
Patent number: 11315884Abstract: A method of forming alignment marks includes providing a III-V compound substrate having a device region and an alignment mark region, forming a hardmask layer having a first set of openings on the alignment mark region exposing a first surface portion of the III-V compound substrate and a second set of openings on the device region exposing a second surface portion of the III-V compound substrate, etching the exposed surface of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches, and epitaxially regrowing a semiconductor layer in the trenches to form the alignment marks extending to a predetermined height over the processing surface of the III-V compound substrate.Type: GrantFiled: July 15, 2020Date of Patent: April 26, 2022Assignee: NEXGEN POWER SYSTEMS, INC.Inventors: Clifford Drowley, Ray Milano, Robert Routh, Subhash Srinivas Pidaparthi, Andrew P. Edwards
-
Publication number: 20220020743Abstract: A method for manufacturing a vertical FET device includes providing a semiconductor substrate structure including a semiconductor substrate and a first semiconductor layer coupled to the semiconductor substrate. The first semiconductor layer is characterized by a first conductivity type. The method also includes forming a plurality of semiconductor fins coupled to the first semiconductor layer. Each of the plurality of semiconductor fins is separated by one of a plurality of recess regions. The method further includes epitaxially regrowing a semiconductor gate layer including a surface region in the plurality of recess regions. The method also includes forming an isolation region within the surface region of the semiconductor gate layer. The isolation region surrounds each of the plurality of semiconductor fins. The method includes forming a source contact structure coupled to each of the plurality of semiconductor fins and forming a gate contact structure coupled to the semiconductor gate layer.Type: ApplicationFiled: July 12, 2021Publication date: January 20, 2022Applicant: NEXGEN POWER SYSTEMS, INC.Inventors: Clifford Drowley, Hao Cui, Andrew P. Edwards, Subhash Srinivas Pidaparthi
-
Publication number: 20220013626Abstract: A method for manufacturing a semiconductor device includes: providing a semiconductor substrate; epitaxially growing a first semiconductor layer coupled to the semiconductor substrate; epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer comprises a contact region and a terminal region surrounding the contact region; forming a mask layer on the second semiconductor layer, wherein the mask layer is patterned with a tapered region aligned with the terminal region of the second semiconductor layer; implanting ions into the terminal region of the second semiconductor layer using the mask layer to form a tapered junction termination element in the terminal region of the second semiconductor layer; and forming a contact structure in the contact region of the second semiconductor layer.Type: ApplicationFiled: July 7, 2021Publication date: January 13, 2022Applicant: NEXGEN POWER SYSTEMS, INC.Inventors: Subhash Srinivas Pidaparthi, Andrew P. Edwards, Clifford Drowley, Kedar Patel
-
Publication number: 20210407815Abstract: A method of manufacturing a vertical FET device includes providing a semiconductor substrate structure including a marker layer; forming a hardmask layer coupled to the semiconductor substrate structure, wherein the hardmask layer comprises a set of openings operable to expose an upper surface portion of the semiconductor substrate structure; etching the upper surface portion of the semiconductor substrate structure to form a plurality of fins; etching at least a portion of the marker layer; detecting the etching of the at least a portion of the marker layer; epitaxially growing a semiconductor layer in recess regions disposed between adjacent fins of the plurality of fins; forming a source metal layer on each of the plurality of fins; and forming a gate metal layer coupled to the semiconductor layer.Type: ApplicationFiled: June 23, 2021Publication date: December 30, 2021Applicant: NEXGEN POWER SYSTEMS, INC.Inventors: Wayne Chen, Andrew P. Edwards, Clifford Drowley, Subhash Srinivas Pidaparthi
-
Publication number: 20210305404Abstract: A method of forming an alignment contact includes: providing a III-nitride substrate; epitaxially growing a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type; forming a plurality of III-nitride fins on the first III-nitride layer, wherein each the plurality of III-nitride fins is separated by one of a plurality of first recess regions, wherein the plurality of III-nitride fins are characterized by the first conductivity type; epitaxially regrowing a III-nitride source contact portion on each of the plurality of III-nitride fins; and forming a source contact structure on the III-nitride source contact portions.Type: ApplicationFiled: March 24, 2021Publication date: September 30, 2021Applicant: NEXGEN POWER SYSTEMS, INC.Inventors: Clifford Drowley, Andrew P. Edwards, Subhash Srinivas Pidaparthi, Shahin Sharifzadeh
-
Publication number: 20210210624Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a drift layer of the first conductivity type coupled to the semiconductor substrate, a fin array having a first row of fins and a second row of fins on the drift layer, and a space between the first row of fins and the second row of fins. The first row of fins includes a plurality of first elongated fins arranged in parallel to each other along a first row direction and separated by a first distance, and the second row of fins includes a plurality of second elongated fins arranged in parallel to each other along a second row direction and separated by a second distance.Type: ApplicationFiled: December 28, 2020Publication date: July 8, 2021Applicant: NEXGEN POWER SYSTEMS, INC.Inventors: Clifford Drowley, Ray Milano, Subhash Srinivas Pidaparthi, Andrew P. Edwards
-
Publication number: 20210193846Abstract: A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate regionType: ApplicationFiled: December 22, 2020Publication date: June 24, 2021Applicant: NEXGEN POWER SYSTEMS, INC.Inventors: Clifford Drowley, Andrew P. Edwards, Subhash Srinivas Pidaparthi, Ray Milano
-
Publication number: 20210028312Abstract: A transistor includes a substrate having a first surface and a second surface opposite the first surface, a drift region having a doped region on the first surface of the substrate and a graded doping region on the doped region, a semiconductor fin protruding from the graded doping region and comprising a metal compound layer at an upper portion of the semiconductor fin, a source metal contact on the metal compound layer, a gate layer having a bottom portion directly contacting the graded doping region; and a drain metal contact on the second surface of the substrate.Type: ApplicationFiled: July 15, 2020Publication date: January 28, 2021Applicant: NexGen Power Systems, Inc.Inventors: Clifford Drowley, Ray Milano, Subhash Srinivas Pidaparthi, Andrew P. Edwards, Hao Cui, Shahin Sharifzadeh
-
Patent number: 9484470Abstract: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material.Type: GrantFiled: August 24, 2015Date of Patent: November 1, 2016Assignee: Avogy, Inc.Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Richard J. Brown, Donald R. Disney
-
Patent number: 9450112Abstract: A Schottky diode and method of fabricating the Schottky diode using gallium nitride (GaN) materials is disclosed. The method includes providing an n-type GaN substrate having first and second opposing surfaces. The method also includes forming an ohmic metal contact electrically coupled to the first surface, forming an n-type GaN epitaxial layer coupled to the second surface, and forming an n-type aluminum gallium nitride (AlGaN) surface layer coupled to the n-type GaN epitaxial layer. The AlGaN surface layer has a thickness which is less than a critical thickness, and the critical thickness is determined based on an aluminum mole fraction of the AlGaN surface layer. The method also includes forming a Schottky contact electrically coupled to the n-type AlGaN surface layer, where, during operation, an interface between the n-type GaN epitaxial layer and the n-type AlGaN surface layer is substantially free from a two-dimensional electron gas.Type: GrantFiled: September 8, 2014Date of Patent: September 20, 2016Assignee: Avogy, Inc.Inventors: Richard J. Brown, Thomas R. Prunty, David P. Bour, Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, Madhan Raj
-
Patent number: 9397186Abstract: An MPS diode includes a III-nitride substrate characterized by a first conductivity type and a first dopant concentration and having a first side and a second side. The MPS diode also includes a III-nitride epitaxial structure comprising a first III-nitride epitaxial layer coupled to the first side of the substrate, wherein a region of the first III-nitride epitaxial layer comprises an array of protrusions. The III-nitride epitaxial structure also includes a plurality of III-nitride regions of a second conductivity type, each partially disposed between adjacent protrusions. Each of the plurality of III-nitride regions of the second conductivity type comprises a first section laterally positioned between adjacent protrusions and a second section extending in a direction normal to the first side of the substrate. The MPS diode further includes a first metallic structure electrically coupled to one or more of the protrusions and to one or more of the second sections.Type: GrantFiled: January 21, 2015Date of Patent: July 19, 2016Assignee: Avogy, Inc.Inventors: Madhan M. Raj, Brian Alvarez, David P. Bour, Andrew P. Edwards, Hui Nie, Isik C. Kizilyalli
-
Publication number: 20160190351Abstract: A vertical field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.Type: ApplicationFiled: October 19, 2015Publication date: June 30, 2016Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, David P. Bour, Richard J. Brown, Thomas R. Prunty
-
Publication number: 20160190296Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.Type: ApplicationFiled: September 14, 2015Publication date: June 30, 2016Inventors: Linda Romano, Andrew P. Edwards, Richard J. Brown, David P. Bour, Hui Nie, Isik C. Kizilyalli, Thomas R. Prunty, Madhan M. Raj
-
Patent number: 9330918Abstract: A method of making an edge terminated semiconductor device includes providing a GaN substrate having a GaN epitaxial layer grown thereon and exposing a portion of the GaN epitaxial layer to ion implantation. The energy dose is selected to provide a resistivity that is at least 90% of maximum achievable resistivity. The method also includes depositing a conductive layer over a portion of the implanted region.Type: GrantFiled: December 2, 2014Date of Patent: May 3, 2016Assignee: Avogy, Inc.Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, David P. Bour, Richard J. Brown, Thomas R. Prunty
-
Patent number: 9324844Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source.Type: GrantFiled: January 23, 2015Date of Patent: April 26, 2016Assignee: Avogy, Inc.Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, David P. Bour, Richard J. Brown, Thomas R. Prunty