Abstract: Example implementations relate to managing data on a memory module. Data may be transferred between a first NVM and a second NVM on a memory module. The second NVM may have a higher memory capacity and a longer access latency than the first NVM. A mapping between a first address and a second address may be stored in an NVM on the memory module. The first address may refer to a location at which data is stored in the first NVM. The second address may refer to a location, in the second NVM, from which the data was copied.

Abstract: Systems and methods for dynamically and programmatically controlling hardware and software to optimize bandwidth and latency across partitions in a computing system are discussed herein. In various embodiments, performance within a partitioned computing system may be monitored and used to automatically reconfigure the computing system to optimize aggregate bandwidth and latency. Reconfiguring the computing system may comprise reallocating hardware resources among partitions, programming firewalls to enable higher bandwidth for specific inter-partition traffic, switching programming models associated with individual partitions, starting additional instances of one or more applications running on the partitions, and/or one or more other operations to optimize the overall aggregate bandwidth and latency of the system.

Abstract: Example implementations relate to an apparatus to support providing a computing service to a client including transferring control between a primary data processing system and a secondary data processing system in response to an event; the primary data processing system comprising a processor and associated memory and the secondary data processing system comprising a processor and associated memory; the apparatus comprising: circuitry to identify restoration data; the restoration data comprising at least data associated with at least one predetermined type of memory operation of the memory associated with the primary data processing system, and circuitry to output any identified restoration data for storage in the memory associated with the processor of the secondary data processing system.

Abstract: In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.

Abstract: A node for a computing system may include a memory module, a main node processor and a management processor. The memory module may include a non-volatile memory, a module memory controller having a main bus interface for connection to a main bus and a management device providing access to the non-volatile memory through a sideband management bus. The main node processor is connected to the module memory controller and has a main bus interface for connection to a main bus. The management processor has a sideband interface for connection to the sideband management bus. The sideband management processor detects a failure of the node and, in response thereto, copies data from the non-volatile memory of the memory module to another node across the sideband management bus.

Abstract: Systems and methods for dynamically modifying coherence domains are discussed herein. In various embodiments, a hardware controller may be provided that is configured to automatically recognize application behavior and dynamically reconfigure coherence domains in hardware and software to tradeoff performance for reliability and scalability. Modifying the coherence domains may comprise repartitioning the system based on cache coherence independently of one or more software layers of the system. Memory-driven algorithms may be invoked to determine one or more dynamic coherence domain operations to implement. In some embodiments, declarative policy statements may be received from a user via one or more interfaces associated with the controller. The controller may be configured to dynamically adjust cache coherence policy based on the declarative policy statements received from the user.

Abstract: Systems and methods for dynamically and programmatically controlling hardware and software to optimize bandwidth and latency across partitions in a computing system are discussed herein. In various embodiments, performance within a partitioned computing system may be monitored and used to automatically reconfigure the computing system to optimize aggregate bandwidth and latency. Reconfiguring the computing system may comprise reallocating hardware resources among partitions, programming firewalls to enable higher bandwidth for specific inter-partition traffic, switching programming models associated with individual partitions, starting additional instances of one or more applications running on the partitions, and/or one or more other operations to optimize the overall aggregate bandwidth and latency of the system.

Abstract: Systems and methods for dynamically modifying coherence domains are discussed herein. In various embodiments, a hardware controller may be provided that is configured to automatically recognize application behavior and dynamically reconfigure coherence domains in hardware and software to tradeoff performance for reliability and scalability. Modifying the coherence domains may comprise repartitioning the system based on cache coherence independently of one or more software layers of the system. Memory-driven algorithms may be invoked to determine one or more dynamic coherence domain operations to implement. In some embodiments, declarative policy statements may be received from a user via one or more interfaces associated with the controller. The controller may be configured to dynamically adjust cache coherence policy based on the declarative policy statements received from the user.

Abstract: A computing system can include a processor and a persistent main memory including a fault tolerance capability. The computing system can also include a memory controller to store data in the persistent main memory and create redundant data. The memory controller can also store the redundant data remotely with respect to the persistent main memory. The memory controller can further access the redundant data during failure of the persistent main memory.

Abstract: Example implementations relate to an apparatus to support providing a computing service to a client including transferring control between a primary data processing system and a secondary data processing system in response to an event; the primary data processing system comprising a processor and associated memory and the secondary data processing system comprising a processor and associated memory; the apparatus comprising: circuitry to identify restoration data; the restoration data comprising at least data associated with at least one predetermined type of memory operation of the memory associated with the primary data processing system, and circuitry to output any identified restoration data for storage in the memory associated with the processor of the secondary data processing system.

Abstract: In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.

Abstract: A node for a computing system may include a memory module, a main node processor and a management processor. The memory module may include a non-volatile memory, a module memory controller having a main bus interface for connection to a main bus and a management device providing access to the nonvolatile memory through a sideband management bus. The main node processor is connected to the module memory controller and has a main bus interface for connection to a main. The management processor has a side band interface for connection to the side band management bus. The side band management processor detects a failure of the node and, in response thereto, copies data from the non-volatile memory of the memory module to another node across the side band management bus.

Abstract: Example implementations relate to a method of tracking data in a non-volatile memory device (NVM) device. A meta-data block from the NVM device is obtained, where the meta-data block includes meta-data. The meta-data block from the NVM device is used to track an associated data object, meta-data in the data block, a user data block, a meta-data block, or an additional data block. The meta-data block from the NVM device is used to point to the associated data object, the meta-data in the data block, the user data block, the meta-data block, or the additional data block. The meta-data block from the NVM device is further used to link the associated data object, the meta-data in the data block, the user data block, the meta-data block, or the additional data block.

Abstract: A system and method for recovering stranded data from a non-volatile memory is provided. An example of a method includes copying data from a non-volatile memory (NVM) in a home node over a sideband interface and writing the data to a target memory region, wherein the target memory region is in a fail-over node.

Abstract: A unifying memory controller (UMC) to send and receive data to and from a local host. The UMC also may manage data placement and retrieval by using an address mapper. The UMC may also selectively provide power to a plurality of memory locations. The UMC may also manage data placement based on a policy that can make use of a property stored in the metadata storage location. The property may be a property describing the data that is being managed. The UMC also may use its own local cache that may store copies of data managed by the circuit.

Abstract: In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.

Abstract: Example implementations relate to a method of tracking data in a non-volatile memory device (NVM) device. A meta-data block from the NVM device is obtained, where the meta-data block includes meta-data. The meta-data block from the NVM device is used to track an associated data object, meta-data in the data block, a user data block, a meta-data block, or an additional data block. The meta-data block from the NVM device is used to point to the associated data object, the meta-data in the data block, the user data block, the meta-data block, or the additional data block. The meta-data block from the NVM device is further used to link the associated data object, the meta-data in the data block, the user data block, the meta-data block, or the additional data block.

Abstract: A unifying memory controller (UMC) to send and receive data to and from a local host. The UMC also may manage data placement and retrieval by using an address mapper. The UMC may also selectively provide power to a plurality of memory locations. The UMC may also manage data placement based on a policy that can make use of a property stored in the metadata storage location. The property may be a property describing the data that is being managed. The UMC also may use its own local cache that may store copies of data managed by the circuit.

Abstract: Example implementations relate to managing data on a memory module. Data may be transferred between a first NVM and a second NVM on a memory module. The second NVM may have a higher memory capacity and a longer access latency than the first NVM. A mapping between a first address and a second address may be stored in an NVM on the memory module. The first address may refer to a location at which data is stored in the first NVM. The second address may refer to a location, in the second NVM, from which the data was copied.

Abstract: Example embodiments relate to response control for memory modules that include or interface with non-compliant memory technologies. A memory module may include an interface to a memory bus that complies with a data transfer standard, wherein the memory bus communicates with a memory controller, and an interface to a non-compliant memory technology that does not comply with the data transfer standard. The memory module may include a command monitoring circuit to determine whether a command from the memory controller has been or will be completed by the non-compliant memory circuit within a defined amount of time within which a command should be completed according to the data transfer standard. The memory module may include an error causing circuit that signals to the memory controller or an operating system when the command has not or will not complete within the defined amount of time.