Patents by Inventor Andrew R. Wheeler
Andrew R. Wheeler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160147620Abstract: A computing system can include a processor and a persistent main memory including a fault tolerance capability. The computing system can also include a memory controller to store data in the persistent main memory and create redundant data. The memory controller can also store the redundant data remotely with respect to the persistent main memory. The memory controller can further access the redundant data during failure of the persistent main memory.Type: ApplicationFiled: June 28, 2013Publication date: May 26, 2016Inventors: Gregg B. Lesartre, Dale C. Morris, Gary Gostin, Russ W. Herrell, Andrew R. Wheeler, Blaine D. Gaither
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Publication number: 20160139807Abstract: Example embodiments relate to write flow control for memory modules that include or interface with non-compliant memory technologies. A memory module may include an interface to a memory bus and a memory controller that comply with a data transfer standard. The memory module may include a write buffer to receive write commands from the interface to the memory bus. The write buffer may cause the write commands to be transmitted to the non-compliant memory technology using a communication protocol that does not comply with the data transfer standard. The memory module may include a flow control credit counter to monitor the capacity of the write buffer, and to provide a credit count to the memory controller that indicates the number of write commands that the write buffer can accept.Type: ApplicationFiled: July 9, 2013Publication date: May 19, 2016Applicant: Hewlett-Packard Development Company, L.P.Inventors: Gregg B. LESARTRE, Andrew R. WHEELER
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Publication number: 20160132413Abstract: A system and method for recovering stranded data from a non-volatile memory is provided. An example of a method includes copying data from a non-volatile memory (NVM) in a home node over a sideband interface and writing the data to a target memory region, wherein the target memory region is in a fail-over node.Type: ApplicationFiled: July 30, 2013Publication date: May 12, 2016Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Andrew R. Wheeler, Gregg B. Lesartre
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Publication number: 20160034392Abstract: A method for sending data from a local memory device in a first computing device to an external memory device in a second computing device is described herein. In one example, a method includes configuring the local memory device to store data for the external memory device and detecting a request for data from the external memory device. The method also includes translating a memory address that corresponds to the requested data from an external memory address to a local memory address. Additionally, the method includes retrieving the requested data based on the local memory address and sending the requested data to the second computing device.Type: ApplicationFiled: March 28, 2013Publication date: February 4, 2016Inventors: Gregg B. Lesartre, Andrew R. Wheeler, Russ W. Herrell
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Patent number: 9207990Abstract: A method and system for migrating at least one critical resource during a migration of an operative portion of a computer system are disclosed. In at least some embodiments, the method includes (a) sending first information constituting a substantial copy of a first of the at least one critical resource via at least one intermediary between a source component and a destination component. The method further includes (b) transitioning a status of the destination component from being incapable of receiving requests to being capable of receiving requests, and (c) re-programming an abstraction block to include modified addresses so that at least one incoming request signal is forwarded to the destination component rather than to the source component.Type: GrantFiled: September 28, 2007Date of Patent: December 8, 2015Assignee: Hewlett-Packard Development Company, L.P.Inventors: Chris M. Giles, Russ W. Herrell, John A. Morrison, John R. Planow, Joseph F. Orth, Gerald J. Kaufman, Jr., Andrew R. Wheeler, Daniel Zilavy
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Publication number: 20150074316Abstract: In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.Type: ApplicationFiled: April 30, 2012Publication date: March 12, 2015Inventors: Blaine D. Gaither, Robert J. Brooks, Benjamin D. Osecky, Kathryn A. Evertson, Andrew R. Wheeler, David Fisk
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Patent number: 8782779Abstract: A system and method for achieving one or more protected regions within a computer system having multiple partitions are disclosed. In at least some embodiments, the system includes an intermediary device for use within the computer system having the multiple partitions. The intermediary device includes a fabric device, and a first firewall device capable of limiting communication of a signal based upon at least one of a source of the signal and an intended destination of the signal, the first firewall device being at least indirectly coupled to the fabric device. The intermediary device further includes a first conversion device that is one of integrated with the first firewall device and distinct from the first firewall device, and that is capable of converting between a processor address and a fabric address for use by the fabric device. In some embodiments, the various devices each include Control and Status Registers (CSRs).Type: GrantFiled: September 26, 2007Date of Patent: July 15, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Chris M. Giles, Russ W. Herrell, John A. Morrison, Andrew R. Wheeler, Gerald J. Kaufman, Jr., Leith L. Johnson, Daniel Zilavy
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Patent number: 8612973Abstract: A method and system for handling interrupts within a computer system during hardware resource migration are disclosed. In at least some embodiments, the method includes (a) programming an address conversion component so that incoming interrupt signals are directed to a control component rather than to a source processing resource, and (b) accumulating the incoming interrupt signals at the control component. Additionally the method also includes, subsequent to the migration of the partition from the source processing resource to a destination processing resource, (c) sending the accumulated incoming interrupt signals to the destination processing resource, and (d) reprogramming the address conversion component so that further incoming interrupt signals are directed to the destination processing resource.Type: GrantFiled: September 26, 2007Date of Patent: December 17, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: Chris M. Giles, Russ W. Herrell, John A. Morrison, John R. Planow, Joseph F. Orth, Andrew R. Wheeler
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Patent number: 8234459Abstract: A switch module having shared memory that is allocated to other blade servers. A memory controller partitions and enables access to partitions of the shared memory by requesting blade servers.Type: GrantFiled: March 13, 2009Date of Patent: July 31, 2012Assignee: Hewlett-Packard Development Company, L.P.Inventors: Blaine D. Gaither, Andrew R. Wheeler
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Patent number: 8001310Abstract: A scalable computer node includes a first central processing unit (CPU), a memory subsystem, and a socket that is configured to receive a second CPU. An expansion module is mounted in the socket instead of the second CPU, where the expansion module is socket-compatible with the second CPU. The expansion module has a CPU interface to communicate with the first CPU, a memory interface to communicate with the memory subsystem, and a fabric interface to communicate over a communications fabric with an expansion electronic subsystem to expand a capacity of the computer node.Type: GrantFiled: March 4, 2009Date of Patent: August 16, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Andrew R. Wheeler, Mark E. Shaw
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Patent number: 7856549Abstract: A system for dynamically regulating power consumption in an information technology (IT) infrastructure having a plurality of compute nodes interconnected over a network is provided. The system includes at least one virtual machine (VM) host deployed at each of the plurality of compute nodes, the at least one VM host is operable to host at least one VM guest, and the VM hosts on different ones of the plurality of compute nodes are version compatible to enable migration of the VM guests among the VM hosts. The system further includes a management module connected to the plurality of compute nodes over the network to receive a native measurement of a performance metric of a computing resource in each of the plurality of compute nodes, the management module is operable to dynamically regulate power consumption of the plurality of compute nodes by migrating the VM guests among the VM hosts based at least on the received performance metrics of the plurality of compute nodes.Type: GrantFiled: January 24, 2007Date of Patent: December 21, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventor: Andrew R. Wheeler
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Publication number: 20100235562Abstract: A switch module having shared memory that is allocated to other blade servers. A memory controller partitions and enables access to partitions of the shared memory by requesting blade servers.Type: ApplicationFiled: March 13, 2009Publication date: September 16, 2010Inventors: Blaine D. Gaither, Andrew R. Wheeler
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Publication number: 20100228900Abstract: A scalable computer node includes a first central processing unit (CPU), a memory subsystem, and a socket that is configured to receive a second CPU. An expansion module is mounted in the socket instead of the second CPU, where the expansion module is socket-compatible with the second CPU. The expansion module has a CPU interface to communicate with the first CPU, a memory interface to communicate with the memory subsystem, and a fabric interface to communicate over a communications fabric with an expansion electronic subsystem to expand a capacity of the computer node.Type: ApplicationFiled: March 4, 2009Publication date: September 9, 2010Inventors: Andrew R. Wheeler, Mark E. Shaw
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Publication number: 20090089787Abstract: A method and system for migrating at least one critical resource during a migration of an operative portion of a computer system are disclosed. In at least some embodiments, the method includes (a) sending first information constituting a substantial copy of a first of the at least one critical resource via at least one intermediary between a source component and a destination component. The method further includes (b) transitioning a status of the destination component from being incapable of receiving requests to being capable of receiving requests, and (c) re-programming an abstraction block to include modified addresses so that at least one incoming request signal is forwarded to the destination component rather than to the source component.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Inventors: Chris M. Giles, Russ W. Herrell, John A. Morrison, John R. Planow, Joseph F. Orth, Gerald J. Kaufman, JR., Andrew R. Wheeler, Daniel Zilavy
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Publication number: 20090083505Abstract: A system and method for achieving one or more protected regions within a computer system having multiple partitions are disclosed. In at least some embodiments, the system includes an intermediary device for use within the computer system having the multiple partitions. The intermediary device includes a fabric device, and a first firewall device capable of limiting communication of a signal based upon at least one of a source of the signal and an intended destination of the signal, the first firewall device being at least indirectly coupled to the fabric device. The intermediary device further includes a first conversion device that is one of integrated with the first firewall device and distinct from the first firewall device, and that is capable of converting between a processor address and a fabric address for use by the fabric device. In some embodiments, the various devices each include Control and Status Registers (CSRs).Type: ApplicationFiled: September 26, 2007Publication date: March 26, 2009Inventors: Chris M. Giles, Russ W. Herrell, John A. Morrison, Andrew R. Wheeler, Gerald J. Kaufman, JR., Leith L. Johnson, Daniel Zilavy
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Publication number: 20090083467Abstract: A method and system for handling interrupts within a computer system during hardware resource migration are disclosed. In at least some embodiments, the method includes (a) programming an address conversion component so that incoming interrupt signals are directed to a control component rather than to a source processing resource, and (b) accumulating the incoming interrupt signals at the control component. Additionally the method also includes, subsequent to the migration of the partition from the source processing resource to a destination processing resource, (c) sending the accumulated incoming interrupt signals to the destination processing resource, and (d) reprogramming the address conversion component so that further incoming interrupt signals are directed to the destination processing resource.Type: ApplicationFiled: September 26, 2007Publication date: March 26, 2009Applicant: Hewlett-Packard Development Company, L.P.Inventors: Chris M. Giles, Russ W. Herrell, John A. Morrison, John R. Planow, Joseph F. Orth, Andrew R. Wheeler
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Publication number: 20080177424Abstract: A system for dynamically regulating power consumption in an information technology (IT) infrastructure having a plurality of compute nodes interconnected over a network is provided. The system includes at least one virtual machine (VM) host deployed at each of the plurality of compute nodes, the at least one VM host is operable to host at least one VM guest, and the VM hosts on different ones of the plurality of compute nodes are version compatible to enable migration of the VM guests among the VM hosts. The system further includes a management module connected to the plurality of compute nodes over the network to receive a native measurement of a performance metric of a computing resource in each of the plurality of compute nodes, the management module is operable to dynamically regulate power consumption of the plurality of compute nodes by migrating the VM guests among the VM hosts based at least on the received performance metrics of the plurality of compute nodes.Type: ApplicationFiled: January 24, 2007Publication date: July 24, 2008Inventor: Andrew R. Wheeler