Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: A method for executing non-native instructions in a computing system having a processor configured to execute native instructions may include fetching a first non-native instruction from a plurality of non-native instructions; interpreting the first non-native instruction to generate a first instruction code; compiling the first instruction code to generate a first native instruction corresponding to the first non-native instruction; determining whether to execute the first instruction code or the generated first native instruction; and implementing a first virtual machine instruction corresponding to the first non-native instruction based, at least in part, on determining whether to execute the first instruction code or the first native instruction.

Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: A method for executing non-native instructions in a computing system having a processor configured to execute native instructions may include fetching a first non-native instruction from a plurality of non-native instructions; interpreting the first non-native instruction to generate a first instruction code; compiling the first instruction code to generate a first native instruction corresponding to the first non-native instruction; determining whether to execute the first instruction code or the generated first native instruction; and implementing a first virtual machine instruction corresponding to the first non-native instruction based, at least in part, on determining whether to execute the first instruction code or the first native instruction.

Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: Systems and methods for executing nonnative instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process.

Abstract: The disclosure relates generally to managing assignment of tasks among instruction processors (IPs) within a computer system having multiple IPs, and more particularly to binding emulated IPs with a host system's IPs (e.g., processor cores) for facilitating control over affinity-based assignment of tasks among the host system's IPs by a task manager (e.g., OS) that is executing on the emulated IPs, rather than running directly on the host system's IPs. Certain embodiments provide techniques for binding emulated IPs with actual IPs of a computing system that is hosting the emulated IPs, thereby enabling better control of management of the system by a task manager executing on the emulated IPs. For instance, in certain embodiments, a dispatcher (e.g., of an OS running on emulated IPs) performs affinity-based management of task assignment for tasks performed for an application program among IPs of a host system that is hosting the emulated IPs.

Abstract: The disclosure relates generally to managing assignment of tasks among instruction processors (IPs) within a computer system having multiple IPs, and more particularly to binding emulated IPs with a host system's IPs (e.g., processor cores) for facilitating control over affinity-based assignment of tasks among the host system's IPs by a task manager (e.g., OS) that is executing on the emulated IPs, rather than running directly on the host system's IPs. Certain embodiments provide techniques for binding emulated IPs with actual IPs of a computing system that is hosting the emulated IPs, thereby enabling better control of management of the system by a task manager executing on the emulated IPs. For instance, in certain embodiments, a dispatcher (e.g., of an OS running on emulated IPs) performs affinity-based management of task assignment for tasks performed for an application program among IPs of a host system that is hosting the emulated IPs.

Abstract: Approaches for recovering state data between boot sessions of an emulated operating system (OS). An OS is emulated on a host OS. In response to each memory acquire request from the emulated OS, an interface to the host OS returns a memory area for use by the emulated OS and stores allocation data associated with the memory area. The allocation data includes an address referencing the memory area and a boot sequence number that indicates a boot session of the emulated OS. While booting the second emulated OS to a current boot session, the stored allocation data is retrieved from the interface, and in response to the stored allocation data including a selected boot sequence number, data from the memory area referenced by the address in the allocation data is stored in retentive storage by the second OS.

Abstract: Disclosure of approaches for stabilizing an emulated system. In one approach, a first operating system (OS) is executed on an instruction processor, the first OS including instructions native to the instruction processor. A second OS and a plurality of application programs are emulated on the first OS. The second OS polls the first OS for memory statistics of the first OS. The memory statistics indicate a current state of operating parameters of the memory of the data processing system used by the first OS in managing the data processing system. The second OS controls a number of the application programs allowed to execute in response to the memory statistics provided by the first OS to the second OS.

Abstract: A method, a translator, and a computer-readable medium for translating compiled programming code from a first code state to a second code state are disclosed. The programming code in the first state has a plurality of basic blocks, where each basic block has a set of instructions. At least one basic block ends in a dynamic branch, the dynamic branch being a transfer to one of a set of destinations based on a calculation of a destination address. The plurality of basic blocks in the first state of the programming code are identified, as are links between the identified basic blocks. A control flow graph (CFG) of the programming code is then constructed based on the identified basic blocks and identified links, where the CFG is in a preliminary form. At least one basic block ending in a dynamic branch is identified, and all identified basic blocks that lead to the dynamic branch are explored, based on the CFG, as far back as is necessary to fully determine a set of destination addresses for the dynamic branch.

Abstract: A memory management interface is provided to synchronize the operation of two disparate operating systems (OSes) that are executing on the same data processing platform. In one embodiment, the first operating system is a legacy OS of the type that is generally associated with an enterprise-level data processing system such as a mainframe. In contrast, the second OS is of a type designed to execute on commodity hardware such as personal computers. The first OS communicates with the second OS via a control logic interface to establish its execution environment, and to perform memory management functions. This interface supports a two-phase boot process that ensures that all memory allocated to the first OS can be released if an error occurs that affects operations of the first OS. This prevents the development of memory leaks.

Abstract: An emulation system, computer program product, and method for emulating the execution of a target program comprising instructions of an instruction set of a target computer on a host computer having a different instruction set operate by performing a static translation of the instructions of the target program into a series of instructions of an intermediate instruction set, the intermediate instruction set being optimized for interpretation on the host computer, and then executing the series of instructions of the intermediate instruction set by interpretation on the host computer.

Abstract: A method, a translator, and a computer-readable medium for translating compiled programming code from a first code state to a second code state are disclosed. The programming code in the first state has a plurality of basic blocks, where each basic block has a set of instructions. At least one basic block ends in a dynamic branch, the dynamic branch being a transfer to one of a set of destinations based on a calculation of a destination address. The plurality of basic blocks in the first state of the programming code are identified, as are links between the identified basic blocks. A control flow graph (CFG) of the programming code is then constructed based on the identified basic blocks and identified links, where the CFG is in a preliminary form. At least one basic block ending in a dynamic branch is identified, and all identified basic blocks that lead to the dynamic branch are explored, based on the CFG, as far back as is necessary to fully determine a set of destination addresses for the dynamic branch.

Abstract: An emulation system functions to translate instructions comprising a target application of a target system into corresponding instructions native to a host system and executes the instructions on the host system. During execution, the emulation system encounters target disk read/write operations. As the memory architectures of the host and target computer systems differ, the data in host memory is conformed to a target memory format when data in keyboard memory buffer is processed. Also, the host and target disk controllers cause storage of data on diskettes in differing byte orders. However, the emulation system performs disk/read write operations without byte-reversal prior to disk-write or subsequent to disk read operations. Thus, the host does not produce storage media having data conforming to that of target storage media.