Abstract: A first dynamic link library (DLL) of a first computing environment, which exports one or more procedures that an application program executing in the first computing environment can call, is replaced with a second DLL that executes in a second computing environment, in a manner that is transparent to the calling application. A source code skeleton of the second DLL is automatically generated based on information contained in a directory of the compiled object code of the first DLL. The exported procedures of the second DLL have interfaces that are identical (from the perspective of the calling application) to the interfaces of the corresponding exported procedures of the first DLL, but the exported procedures of the second DLL comprise native code of the second computing environment.

Abstract: A method for communicating active messages among nodes of a parallel processing computer system is disclosed. The active messages are defined by .mu.threads, and the method comprises the steps of: (a) generating a .mu.thread comprising an instruction pointer, frame pointer, and Local Parameters pointer from a first node to a second node; and (b) performing a procedure on a data structure in accordance with the .mu.thread. The instruction pointer points to an application specific procedure in system memory, and the frame pointer points to an application specific data structure in system memory. The Local Parameters pointer points to one or more words of additional data or parameters stored in memory mapped device registers or system memory.

Abstract: A block structured data processing system concatenates block structured code so as to expedite the execution of less structured language code. The concatenation is performed in a code unit for a parallel pipeline processor so that the concatenated code can be executed in parallel. To optimize the access to the data associated with address couples, an address couple associative memory (ACAM) is provided for the translation of conventional address couples found in block structured systems into general registers numbers. The mechanism attempts to keep data in the general registers thus removing the requirement to re-fetch it from the memory system. To expedite the fetching of data arrays, descriptors may be stored in ACAM for use in continuously accessing data arrays in memory.

Abstract: A computer system executes steps to provide results in an order different from an intended order. Instructions are concatenated into a plurality of jobs. Different invocations of a variable within the computer instruction stream may be assigned respectively different storage locations and each storage location may correspond to a different job. When all the storage locations associated with a particular job indicate available resources (e.g. valid variable input), the job may be executed. A mechanism allows for job re-execution, if needed, due to interrupt or error.

Abstract: A memory system provides a method for error detection and correction. Large data words are divided into multiple error correction zones. One zone from each of two or more words are combined to form an error domain. Address bits are also included in the domains. Check bits are generated from the data bits in each domain and stored with the data. During data retrieval, each domain is processed separately, generating a syndrome for each domain. The syndromes provide indication of bit errors, allowing the correction of a single-bit error in each domain. Multiple-bit errors may thus be corrected within each word using a single-bit error correction code. Data are distributed in physical memory so that, within each domain, no more than one data bit is stored in the same memory device. This method provides full error correction capability in the presence of a catastrophic memory package failure, so long as failures in multiple packages do not cause multiple errors within a single error correction domain.

Abstract: An array of various types of processors for the purpose of simulating computer functions for large computer systems. These functions may vary from simple AND, OR and other functions to large arithmetic logic units and even random access memories. The simulation array is a tree-type array where the leaves of the tree are the actual logic simulation processors with the other processors serving as nodes which route change of value notices among the various logic simulation processors.

Abstract: A task control mechanism for maintaining a queue of ready or available processes linked together according to an assigned priority for a plurality of central processors where the processors may be assigned to the highest priority task when that processor is not busy executing some higher priority task. The task control mechanism also includes a mechanism for computing task priorities as new tasks are inserted into the queue or removed. The mechanism also maintains an event table which is really a table of event designations to be allocated to different processes upon request where the requesting processes assign a particular function or "meaning" to the event designation. The mechanism of the present invention maintains the state of such allocated events in the event table and signals the related (or "waiting") processes that an event has happened so that the particular system central processors assigned to execute those particular processes may then proceed with their execution.

Abstract: An event allocation mechanism in a processing system which mechanism maintains an event table which is really a table of event designations to be allocated to different processes upon request where the requesting processes assign a particular function or "meaning" to the event designation. The mechanism of the present invention maintains the state of such allocated events in the event table and signals the related (or "waiting") processes that an event has happened so that the particular system central processors assigned to execute those particular processes may then proceed with their execution.