Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The control circuitry selects an impedance level for the first and second resistive structures, and detect coupling of a remote receiver to the transmitter through interconnects and detect decoupling of the remote receiver from the transmitter. Other embodiments are described and claimed.

Abstract: In some embodiments, a chip comprises control circuitry to provide inband signals, inband output ports, and transmitters to transmit the inband signals to the inband output ports. The control circuitry selectively includes loopback initiating commands in the inband signals. Other embodiments are described and claimed.

Abstract: A distributed power management system for a bus architecture or similar communications network. The system supports multiple low power states and defines entry and exit procedures for maximizing energy savings and communication speed.

Abstract: In some embodiments, a chip comprising transmitters, local receivers, and control circuitry to determine whether the transmitters are coupled to remote receivers through interconnects. If certain conditions are met the control circuitry causes the transmitters to transmit a compliance test pattern on the interconnects. The conditions include that the control circuitry determines that the remote receivers are coupled to the transmitters and the local receivers have not received signals within a particular time. Other embodiments are described and claimed.

Abstract: An apparatus and method for low latency power management on a serial data link are described. In one embodiment, the method includes the detection of an electrical idle exit condition during receiver operation in an electrical idle state. Once detected, data synchronization is performed according to one or more received data synchronization training patterns. Finally, when the synchronization is performed within a determined synchronization re-establishment period, the receiver will resume operation according to a normal power state. Accordingly, the embodiment described illustrates an open loop, low latency power resumption operation for power management within 3GIO links.

Abstract: Interference within a wireless apparatus is mitigated by adjusting one or more transmission characteristics associated with an interconnect of the apparatus. In at least one embodiment, the interconnect is a PCI Express interconnect.

Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, a transmitter, change detection circuitry, and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The change detection circuitry detects changes in voltages of the first and second nodes following a change in voltage of the variable voltage source. The control circuitry determines whether the changes in voltages of the first and second nodes are consistent with the transmitter being coupled through interconnects to a remote receiver. Other embodiments are described and claimed.

Abstract: A distributed power management system for a bus architecture or similar communications network. The system supports multiple low power states and defines entry and exit procedures for maximizing energy savings and communication speed.

Abstract: An apparatus and a method for active phase cancellation for an inductor/capacitor network have been disclosed. One embodiment of the apparatus includes a package and a die mounted on the package. The die comprises circuitry to to substantially cancel resonance between an inductance of the package and a capacitance of the die.

Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, a transmitter, change detection circuitry, and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The change detection circuitry detects changes in voltages of the first and second nodes following a change in voltage of the variable voltage source. The control circuitry determines whether the changes in voltages of the first and second nodes are consistent with the transmitter being coupled through interconnects to a remote receiver. Other embodiments are described and claimed.

Abstract: According to one embodiment, a built-in self test (IBIST) architecture/methodology is disclosed. The IBIST provides for testing the functionality of an interconnect (such as a bus) between a transmitter and a receiver component. The IBIST architecture includes a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.

Abstract: In some embodiments, a chip comprises control circuitry to provide inband signals, inband output ports, and transmitters to transmit the inband signals to the inband output ports. The control circuitry selectively includes loopback initiating commands in the inband signals. Other embodiments are described and claimed.

Abstract: The present invention is a method and apparatus to self update a firmware device. A communication interface receives programming information. A parser coupled to the communication interface to parse the programming information into control commands and program data.

Abstract: A computer system's existing video BIOS is updated independently without the need for updating the computer system's entire system BIOS, by transferring a new video BIOS contained on a floppy disk into a flash memory block dedicated for video-BIOS storage. The video-BIOS update mode is entered by initializing the computer and pressing a “hot key sequence” while the computer is being initialized. Once the hot key sequence has been detected, the system BIOS reads the new video BIOS from the floppy disk and performs a security check to ensure that the new video BIOS contained on the floppy disk is known to the system BIOS. The security check involves decoding the digital signature of the new video BIOS with a corresponding public key stored with the system BIOS. Once the security check has been completed, the system BIOS writes the new video BIOS into a dedicated 64K flash-memory block.

Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The control circuitry selects an impedance level for the first and second resistive structures, and detect coupling of a remote receiver to the transmitter through interconnects and detect decoupling of the remote receiver from the transmitter. Other embodiments are described and claimed.

Abstract: A distributed power management system for a bus architecture or similar communications network. The system supports multiple low power states and defines entry and exit procedures for maximizing energy savings and communication speed.

Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, a transmitter, change detection circuitry, and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The change detection circuitry detects changes in voltages of the first and second nodes following a change in voltage of the variable voltage source. The control circuitry determines whether the changes in voltages of the first and second nodes are consistent with the transmitter being coupled through interconnects to a remote receiver. Other embodiments are described and claimed.

Abstract: In some embodiments, a chip comprising transmitters, local receivers, and control circuitry to determine whether the transmitters are coupled to remote receivers through interconnects. If certain conditions are met the control circuitry causes the transmitters to transmit a compliance test pattern on the interconnects. The conditions include that the control circuitry determines that the remote receivers are coupled to the transmitters and the local receivers have not received signals within a particular time. Other embodiments are described and claimed.

Abstract: An apparatus and method for low latency power management on a serial data link are described. In one embodiment, the method includes the detection of an electrical idle exit condition during receiver operation in an electrical idle state. Once detected, data synchronization is performed according to one or more received data synchronization training patterns. Finally, when the synchronization is performed within a determined synchronization re-establishment period, the receiver will resume operation according to a normal power state. Accordingly, the embodiment described illustrates an open loop, low latency power resumption operation for power management within 3GIO links.

Abstract: A memory controller with an integrated system management memory region is disclosed. The memory controller receives an SMI acknowledge signal from a processor. The processor then delivers a system management memory address to the memory controller. Instead of fetching SMI handler instructions from the address indicated by the processor, the memory controller instead fetches SMI handler instructions from its integrated system management memory region. At the end of the integrated system management memory's SMI handler, the processor is instructed to fetch instructions from the address originally specified by the processor. In this manner, a BIOS SMI routine may be executed after the integrated SMI routine is executed.