Patents by Inventor Andrew W. Yeoh
Andrew W. Yeoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955534Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.Type: GrantFiled: December 7, 2022Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Andrew W. Yeoh, Joseph Steigerwald, Jinhong Shin, Vinay Chikarmane, Christopher P. Auth
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Publication number: 20240047556Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.Type: ApplicationFiled: October 18, 2023Publication date: February 8, 2024Inventors: Andrew W. YEOH, Joseph STEIGERWALD, Jinhong SHIN, Vinay CHIKARMANE, Christopher P. AUTH
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Publication number: 20230144607Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.Type: ApplicationFiled: January 5, 2023Publication date: May 11, 2023Inventors: Andrew W. YEOH, Tahir GHANI, Atul MADHAVAN, Michael L. HATTENDORF, Christopher P. AUTH
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Publication number: 20230101723Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.Type: ApplicationFiled: December 7, 2022Publication date: March 30, 2023Inventors: Andrew W. YEOH, Joseph STEIGERWALD, Jinhong SHIN, Vinay CHIKARMANE, Christopher P. AUTH
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Patent number: 11581419Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.Type: GrantFiled: October 26, 2020Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Andrew W. Yeoh, Joseph Steigerwald, Jinhong Shin, Vinay Chikarmane, Christopher P. Auth
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Publication number: 20220336633Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.Type: ApplicationFiled: June 24, 2022Publication date: October 20, 2022Inventors: Andrew W. YEOH, Ilsup JIN, Angelo KANDAS, Michael L. HATTENDORF, Christopher P. AUTH
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Patent number: 11404559Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.Type: GrantFiled: September 21, 2020Date of Patent: August 2, 2022Assignee: Intel CorporationInventors: Andrew W. Yeoh, Ilsup Jin, Angelo Kandas, Michael L. Hattendorf, Christopher P. Auth
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Publication number: 20220149075Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.Type: ApplicationFiled: January 26, 2022Publication date: May 12, 2022Inventors: Ranjith KUMAR, Quan SHI, Mark T. BOHR, Andrew W. YEOH, Sourav CHAKRAVARTY, Barbara A. CHAPPELL, M. Clair WEBB
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Patent number: 11271010Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.Type: GrantFiled: September 20, 2017Date of Patent: March 8, 2022Assignee: Intel CorporationInventors: Ranjith Kumar, Quan Shi, Mark T. Bohr, Andrew W. Yeoh, Sourav Chakravarty, Barbara A. Chappell, M. Clair Webb
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Publication number: 20210234022Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.Type: ApplicationFiled: April 9, 2021Publication date: July 29, 2021Inventors: Andrew W. YEOH, Tahir GHANI, Atul MADHAVAN, Michael L. HATTENDORF, Christopher P. AUTH
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Patent number: 11031487Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.Type: GrantFiled: December 3, 2019Date of Patent: June 8, 2021Assignee: Intel CorporationInventors: Andrew W. Yeoh, Tahir Ghani, Atul Madhavan, Michael L. Hattendorf, Christopher P. Auth
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Patent number: 10943817Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate. Individual ones of the plurality of conductive interconnect lines have an upper surface below an upper surface of the ILD layer. An etch-stop layer is on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines.Type: GrantFiled: July 11, 2019Date of Patent: March 9, 2021Assignee: Intel CorporationInventors: Andrew W. Yeoh, Ruth Brain, Michael L. Hattendorf, Christopher P. Auth
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Publication number: 20210066475Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.Type: ApplicationFiled: October 26, 2020Publication date: March 4, 2021Inventors: Andrew W. YEOH, Joseph STEIGERWALD, Jinhong SHIN, Vinay CHIKARMANE, Christopher P. AUTH
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Publication number: 20210013323Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.Type: ApplicationFiled: September 21, 2020Publication date: January 14, 2021Inventors: Andrew W. YEOH, Ilsup JIN, Angelo KANDAS, Michael L. HATTENDORF, Christopher P. AUTH
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Patent number: 10854731Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.Type: GrantFiled: August 9, 2019Date of Patent: December 1, 2020Assignee: Intel CorporationInventors: Andrew W. Yeoh, Joseph Steigerwald, Jinhong Shin, Vinay Chikarmane, Christopher P. Auth
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Publication number: 20200357823Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.Type: ApplicationFiled: September 20, 2017Publication date: November 12, 2020Inventors: Ranjith KUMAR, Quan SHI, Mark T. BOHR, Andrew W. YEOH, Sourav CHAKRAVARTY, Barbara A. CHAPPELL, M. Clair WEBB
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Patent number: 10818774Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A conductive interconnect line is in a trench in the ILD layer, the conductive interconnect line having a first portion and a second portion, the first portion laterally adjacent to the second portion. A dielectric plug is between and laterally adjacent to the first and second portions of the conductive interconnect line, the dielectric plug comprising a metal oxide material.Type: GrantFiled: December 30, 2017Date of Patent: October 27, 2020Assignee: Intel CorporationInventors: Andrew W. Yeoh, Ilsup Jin, Angelo Kandas, Michael L. Hattendorf, Christopher P. Auth
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Patent number: 10796951Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate. Individual ones of the plurality of conductive interconnect lines have an upper surface below an upper surface of the ILD layer. An etch-stop layer is on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines.Type: GrantFiled: December 30, 2017Date of Patent: October 6, 2020Assignee: Intel CorporationInventors: Andrew W. Yeoh, Ruth Brain, Michael L. Hattendorf, Christopher P. Auth
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Patent number: 10777655Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.Type: GrantFiled: December 30, 2017Date of Patent: September 15, 2020Assignee: Intel CorporationInventors: Andrew W. Yeoh, Joseph Steigerwald, Jinhong Shin, Vinay Chikarmane, Christopher P. Auth
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Publication number: 20200105906Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.Type: ApplicationFiled: December 3, 2019Publication date: April 2, 2020Inventors: Andrew W. YEOH, Tahir GHANI, Atul MADHAVAN, Michael L. HATTENDORF, Christopher P. AUTH