Abstract: A cognitive decision support fleet management and maintenance decision system may comprise a first cognitive decision support system to process information regarding a plurality of platforms and generate a list of condition based response activities and a weighted ranking of the probability of success of each condition based activity. A second cognitive decision support system may be tasked by the first to, and configured to, provide a plurality of ranked courses of action. A third cognitive decision support system may be tasked by the second to, and be configured to, assess resource availability for each condition based response activity. The second cognitive decision support system may be further configured to generate from the list of condition based response activities and the resource availability assessment for each condition based response, a plurality of recommended courses of action for the platform. The courses of action may be weighted according to an order of preference in carrying out each.

Abstract: In one aspect, a ballistic resistant garment includes a front component having a front outer shell a rear component having a rear outer shell, each outer shell including a pair of shoulder extensions. Each front shoulder extension includes a first half of a releasable connector and each rear shoulder extension includes a second half of the releasable connector. A release cable is positioned on the front component. In a first position the release cable maintains engagement between the first half of the releasable connector and the second half of the releasable connector to connect the pair of front shoulder extensions with the pair of rear shoulder extensions to form a neck opening. In a second position, the release cable disengage from the releasable connector to enable the pair of front shoulder extensions to disconnect from the pair of rear shoulder extensions.

Abstract: A method, apparatus and program storage device for providing clocks to multiple frequency domains using a single input clock of variable frequency. Independent clock signals are generated at predetermined clock frequency targets in response to control signals that are based on a determined bus clock frequency.

Abstract: A self-contained backup power source such as a battery is provided for components within an electrically powered device such as a storage controller, photocopier or the like, to maintain diagnostic status data and to power a service indicator aid, or diagnostic indicator, such as an LED. A switch selects the backup power source when a primary power source of the electrically powered device is no longer available to the component, such as when the component is removed from the electrically powered device, the primary power source is disconnected as a safety precaution when servicing or replacing the component, or a higher-level assembly, in which the component is provided, is removed from the electrically powered device. The diagnostic indicator may be powered separately from the data storage device.

Abstract: An apparatus, system, and method are disclosed for mandatory end to end integrity checking. The apparatus may include a compatibility module configured to monitor data from a source and verify integrity information compatibility with a standard, and an integrity module configured to wrap the data from the source with additional integrity information. The system may include a source configured to send data over a network, a target configured to receive data over the network, the apparatus, a main memory module, a storage controller, and a storage device. The method includes monitoring data from a source, verifying integrity information compatibility with a standard, and wrapping the data from the source with additional integrity information.

Abstract: The present invention described hereafter provides a single stage inflator with a disk shaped inflator housing with one initiator having a single initiating squib located in an initiator housing, the initiator housing being offset relative to the centerline of the disk shaped inflator housing.

Abstract: A method, apparatus and program storage device for maintaining data is provided that includes receiving primary data at a first node, receiving mirrored data from a second and third node at the first node, and mirroring data received at the first node to a second and third node.

Abstract: A system and method of error detection for unordered data delivery. A data set is received, the data set including a plurality of data segments, each having a descriptor; a data packet for each of the plurality of data segments, each of the data packets including the data segment and the descriptor for each of the plurality of data segments; and a source cyclic redundancy check (CRC) code for each of the data packets. The source CRC codes are stored as a source CRC table and a received CRC code is computed for a first data packet. It is determined whether the received CRC code for the first data packet is in the source CRC table and the first data packet is used when the received CRC code for the first data packet is in the source CRC table.

Abstract: An apparatus, system and method are disclosed for storing modified data. The apparatus includes a battery source for supplying backup power. The apparatus also includes a memory module for storing data. The memory module includes a backup portion and a non-backup portion. Only the backup portion is backed up by the battery source in the event of a power failure. A data flow module controls data flow into and out of the memory module. The data flow module stores modified data exclusively in the backup portion of the memory module.

Abstract: Provided are a method, system, and program for an adaptor to read and write to system memory. A plurality of blocks of data to write to storage are received at an adaptor. The blocks of data are added to a buffer in the adaptor. A determination is made of pages in a memory device and I/O requests are generated to write the blocks in the buffer to the determined pages, wherein two I/O requests are generated to write to one block split between two pages in the memory device. The adaptor executes the generated I/O requests to write the blocks in the buffer to the determined pages in the memory device.

Abstract: An apparatus, system, and method are disclosed for flushing cache data in a cache system. The apparatus includes a zero module and a flush module. The zero module executes an internal processor instruction to zero out a zero memory segment of a nonvolatile memory and a processor cache in response to a loss of primary power to the processor cache. The flush module flushes modified data from an address in the processor cache to a flush memory segment of the nonvolatile memory before the zero module puts a zero in the address. Advantageously, the zero memory segment is reserved within the memory and used to zero out the processor cache, effectively flushing the existing data from the processor cache to a flush memory segment of the memory.

Abstract: A self-contained backup power source such as a battery is provided for components within an electrically powered device such as a storage controller, photocopier or the like, to maintain diagnostic status data and to power a service indicator aid, or diagnostic indicator, such as an LED. A switch selects the backup power source when a primary power source of the electrically powered device is no longer available to the component, such as when the component is removed from the electrically powered device, the primary power source is disconnected as a safety precaution when servicing or replacing the component, or a higher-level assembly, in which the component is provided, is removed from the electrically powered device. The diagnostic indicator may be powered separately from the data storage device.

Abstract: An apparatus, system, and method are disclosed for securely providing power supply commands. A security feature is added to the remote management of power-on and power-off sequences. The feature allows for multiple controller nodes to receive a command to initiate a power sequence. Each controller node possesses a unique identifier. The nodes compare the received command with received commands of other nodes to confirm that each node received identical power commands. The security feature prevents inadvertent power commands from being received and executed by a single controller node. The unique identifier of each node must be provided before execution of the power command occurs.

Abstract: An apparatus, system, and method are disclosed for data error checking and recovery in a data storage device. A redundancy check module creates a redundancy check for data on a data storage device in a SCSI End-to-End Checking Standard environment and a redundancy check storage module stores the redundancy check in a guard associated with the data.

Abstract: A method, apparatus and program storage device for performing a self-healing cache process is described. At least one error affecting a cache is detected. The cache may have a matching address tag for a fetching operation. Based on the type of error, a self-healing cache process is performed based.

Abstract: A data initiator device designates an initial data tag set for tagging data transfers to thereby attach data tags from the designated set to commands directed to data transfers between the data initiator device and a data target device subsequent to the designation of the initial data tag set. The data transfer commands are issued with the attached data tags from the designated data tag set until an occurrence of a reset error associated with one of the issued data transfer commands. In response to the reset error, the data initiator device designates a different data tag set for tagging data transfers to thereby attach data tags from the newly designated data tag set to commands directed to data transfers between the data initiator device and the data target device subsequent to the designation of the new data tag set.

Abstract: A method, apparatus and program storage device for providing self-quiesced logic for handling an error recovery instruction such as a reset or self-test instruction. For example, during a reset or self test procedure, the logic is isolated without adversely affecting the local processor. Self-quiesced logic processes an error recovery instruction by monitoring the processor interface for an idle condition and withholding access to the local processor. Once the local processor interface has been quiesced and the internal logic paths are idle, the logic will proceed with the reset or self-test.

Abstract: Prefetching data and instructions from a hierarchical memory based upon trajectories and patterns of prior memory fetches. Portions of the data are stored in a slower main memory and are transferred to faster intermediate memory between a requester and the slower main memory. The selected data items are retrieved from the slower main memory into a prefetch read buffer as an intermediate memory prior to any request from the requester for the particular selected and prefetched data. The address and size of the prefetched data is derived from the history, pattern, or trajectory of prior memory reads.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: A diagnostic tracing logger is presented for use in a multithread environment in which diagnostic trace log entries are captured and recorded. The trace logs are composed of sequences of memory addresses used to access instructions and operands, instruction op-codes and register specifiers, sequences of memory addresses, branch instructions or exceptions, the contents of registers or semiconductor memory locations, and the like. In one embodiment, a software module configures a plurality of buffers to capture bus traces, each trace triggered by a specific pattern. A buffer controller manages transfer of diagnostic trace information from the plurality of buffers to a diagnostic log without using processor memory cycles. The trace information is transferred to a selected buffer using a processor cache flush instruction. Diagnostic trace logging facilitates diagnosis of complex system and software interactions without the cost and overhead of prior art trace logging techniques.