Patents by Inventor Andrey Efimov

Andrey Efimov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11681666
    Abstract: Systems and methods for a bouncing replication protocol are described herein. The system can include a replication cluster including a plurality of servers and a master controller that can receive a first request to replicate a first transaction and execute a batching process to replicate the first transaction. The batching process can include selecting a first server for replication of the first transaction, determining that a pending acknowledgement from the selected first server has not been identified, adding the first transaction to a first batch for the first server, and sending the first batch including only the first transaction.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 20, 2023
    Assignee: Oracle International Corporation
    Inventor: Andrey Efimov
  • Patent number: 11522955
    Abstract: Techniques for transferring the state information of resources are provided. A gateway receives requests from clients and directs the requests to a resource. The gateway receives a notification that a first resource being accessed by clients will be replaced by a second resource. The first resource completes an initial transfer of state information and receives a terminal instruction. The first resource completes a final transfer of state information, including the terminal instruction, and the gateway redirects traffic, that is addressed to the first resource, to the second resource.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: December 6, 2022
    Assignee: Oracle International Corporation
    Inventors: Andrey Efimov, Daniel Ricketts
  • Publication number: 20220078233
    Abstract: Techniques for transferring the state information of resources are provided. A gateway receives requests from clients and directs the requests to a resource. The gateway receives a notification that a first resource being accessed by clients will be replaced by a second resource. The first resource completes an initial transfer of state information and receives a terminal instruction. The first resource completes a final transfer of state information, including the terminal instruction, and the gateway redirects traffic, that is addressed to the first resource, to the second resource.
    Type: Application
    Filed: September 9, 2020
    Publication date: March 10, 2022
    Applicant: Oracle International Corporation
    Inventors: Andrey Efimov, Daniel Ricketts
  • Publication number: 20220066996
    Abstract: a first request to replicate a first transaction and execute a batching process to replicate the first transaction. The batching process can include selecting a first server for replication of the first transaction, determining that a pending acknowledgement from the selected first server has not been identified, adding the first transaction to a first batch for the first server, and sending the first batch including only the first transaction. The master controller can receive a second request to replicate a second transaction, execute the batching process with the master controller to replicate the second transaction, which executing of the batching process includes adding the second transaction to a second batch including a plurality of transactions, receive an acknowledgement indicative of completion of replication, and send the second batch upon receipt of the acknowledgement indicative of completion of replication.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 3, 2022
    Applicant: Oracle International Corporation
    Inventor: Andrey Efimov
  • Patent number: 10979363
    Abstract: Techniques for resegmenting a partition in a distributed stream-processing platform are provided. The techniques include receiving a trigger to move a partition of the distributed stream-processing platform from a first broker on a first set of physical resources to a second broker on a second a set of physical resources. In response to the trigger, the partition is allocated on the second broker, and the first broker is configured to redirect, to the second broker, requests for new messages after a last offset in the partition without replicating older messages before the last offset to the second broker. Idempotent produce metadata for the partition from the first broker is then merged into the second broker. Finally, metadata for processing requests for the partition is updated to include the second broker.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: April 13, 2021
    Assignee: Oracle International Corporation
    Inventors: Andrey Efimov, John Christopher Petry, Julien Nicolas Dollon, Nathaniel Martin Glass
  • Publication number: 20200195572
    Abstract: Techniques for resegmenting a partition in a distributed stream-processing platform are provided. The techniques include receiving a trigger to move a partition of the distributed stream-processing platform from a first broker on a first set of physical resources to a second broker on a second a set of physical resources. In response to the trigger, the partition is allocated on the second broker, and the first broker is configured to redirect, to the second broker, requests for new messages after a last offset in the partition without replicating older messages before the last offset to the second broker. Idempotent produce metadata for the partition from the first broker is then merged into the second broker. Finally, metadata for processing requests for the partition is updated to include the second broker.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Applicant: Oracle International Corporation
    Inventors: Andrey Efimov, John Christopher Petry, Julien Nicolas Dollon, Nathaniel Martin Glass
  • Patent number: 10608951
    Abstract: Techniques for resegmenting a partition in a distributed stream-processing platform are provided. The techniques include receiving a trigger to move a partition of the distributed stream-processing platform from a first broker on a first set of physical resources to a second broker on a second a set of physical resources. In response to the trigger, the partition is allocated on the second broker, and the first broker is configured to redirect, to the second broker, requests for new messages after a last offset in the partition without replicating older messages before the last offset to the second broker. Idempotent produce metadata for the partition from the first broker is then merged into the second broker. Finally, metadata for processing requests for the partition is updated to include the second broker.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: March 31, 2020
    Assignee: Oracle International Corporation
    Inventors: Andrey Efimov, John Christopher Petry, Julien Nicolas Dollon, Nathaniel Martin Glass
  • Patent number: 10514927
    Abstract: A processor includes logic to execute an instruction stream out-of-order. The instruction stream is divided into a plurality of strands and its instructions and those within the streams are ordered by program order (PO). The processor further includes logic to identify an oldest undispatched instruction in the instruction stream and record its associated PO as an executed instruction pointer, identify a most recently committed store instruction in the instruction stream and record its associated PO as a store commitment pointer, a search pointer with PO less than the execution instruction pointer, identify a first set of store instructions in a store buffer with PO less than the search pointer and eligible for commitment, evaluate whether the first set of store instructions is larger than a number of read ports of the store buffer, and adjust the search pointer.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Anton Lechanka, Andrey Efimov, Sergey Y. Shishlov, Andrey Kluchnikov, Kamil Garifullin, Igor Burovenko, Boris A. Babayan
  • Publication number: 20190104082
    Abstract: Techniques for resegmenting a partition in a distributed stream-processing platform are provided. The techniques include receiving a trigger to move a partition of the distributed stream-processing platform from a first broker on a first set of physical resources to a second broker on a second a set of physical resources. In response to the trigger, the partition is allocated on the second broker, and the first broker is configured to redirect, to the second broker, requests for new messages after a last offset in the partition without replicating older messages before the last offset to the second broker. Idempotent produce metadata for the partition from the first broker is then merged into the second broker. Finally, metadata for processing requests for the partition is updated to include the second broker.
    Type: Application
    Filed: February 28, 2018
    Publication date: April 4, 2019
    Applicant: Oracle International Corporation
    Inventors: Andrey Efimov, John Christopher Petry, Julien Nicolas Dollon, Nathaniel Martin Glass
  • Publication number: 20160364239
    Abstract: A processor includes logic to execute an instruction stream out-of-order. The instruction stream is divided into a plurality of strands and its instructions and those within the streams are ordered by program order (PO). The processor further includes logic to identify an oldest undispatched instruction in the instruction stream and record its associated PO as an executed instruction pointer, identify a most recently committed store instruction in the instruction stream and record its associated PO as a store commitment pointer, a search pointer with PO less than the execution instruction pointer, identify a first set of store instructions in a store buffer with PO less than the search pointer and eligible for commitment, evaluate whether the first set of store instructions is larger than a number of read ports of the store buffer, and adjust the search pointer.
    Type: Application
    Filed: March 27, 2014
    Publication date: December 15, 2016
    Inventors: Anton Lechenko, Andrey Efimov, Sergey Y. Shishlov, Andrey Kluchnikov, Kamil Garifullin, Igor Burovenko, Boris A. Babayan
  • Patent number: 9516335
    Abstract: A method and system may include an interface to receive a video signal and an encoder to compress the video signal on a per-slice basis. In one example, compression of the video signal involves the use (50) of a hash value and an allowable distortion of each slice to select (56) a quantization parameter for the slice. The selected quantization parameter can be used to encode (58) the slice. In addition, a processor can manage wireless transmission of the compressed video signal.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: December 6, 2016
    Assignee: Intel Corporation
    Inventors: Vladislav Chernyshev, Andrey Efimov, Evgeny Belyaev, Mikhail Tsvetkov
  • Publication number: 20160306742
    Abstract: A processor includes a Level-2 (L2) cache, a first and second cluster of execution units, and a first and second data cache unit (DCU) communicatively coupled to the respective clusters of execution units and to the L2 cache. The DCUs each include a data cache and logic to receive a memory operation from an execution unit, respond to the memory operation with information from the data cache when the information is available in the data cache, and retrieve the information from the L2 cache when the information is unavailable in the data cache. The processor further includes logic to maintain contents of the data cache of the first DCU as equal to contents of the data cache of the second DCU at all clock cycles of operation of the processor.
    Type: Application
    Filed: December 23, 2013
    Publication date: October 20, 2016
    Inventors: Anton W. LECHENKO, Andrey EFIMOV, Sergey Y. SHISHLOV, Jayesh IYER, Boris A. BABAYAN
  • Publication number: 20130064289
    Abstract: A method and system may include an interface to receive a video signal and an encoder to compress the video signal on a per-slice basis. In one example, compression of the video signal involves the use (50) of a hash value and an allowable distortion of each slice to select (56) a quantization parameter for the slice. The selected quantization parameter can be used to encode (58) the slice. In addition, a processor can manage wireless transmission of the compressed video signal.
    Type: Application
    Filed: December 24, 2009
    Publication date: March 14, 2013
    Inventors: Vladislav Chernyshev, Andrey Efimov, Evgeny Belyaev, Mikhail Tsvetkov
  • Publication number: 20120293731
    Abstract: A macroblock-scanned picture may be shown directly on a thin film transistor liquid crystal display in macroblock scan order. This enables eliminating conversion operation from macroblock raster scan to line scan order that requires expensive and power-hungry memory for a frame buffer, in some embodiments, which results in a cost savings.
    Type: Application
    Filed: November 24, 2009
    Publication date: November 22, 2012
    Inventors: Mikhail S. Tsvetkov, Andrey Efimov, Eugeniy A. Belyaev
  • Patent number: 8127214
    Abstract: A unified decoder is capable of decoding data encoded with convolutional codes, Turbo codes, and LDPC codes. In at least one embodiment, a unified decoder is implemented within a multi-standard wireless device.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: February 28, 2012
    Assignee: Intel Corporation
    Inventors: Alexey Trofimenko, Andrey Efimov, Andrey V Belogolovy, Vladislav A Chernyshev
  • Patent number: 8091004
    Abstract: An integrated incremental redundancy symbol mapping diversity system for a communication device. The integrated incremental redundancy symbol mapping diversity system includes a transmitter. The transmitter packetizes a retransmission packet according to a modulation scheme in response to a retransmission request from the receiver. The transmitter includes an output packet processor and an inter-packet selective symbol mapper. The output packet processor determines a transmission iteration of a bit segment of the retransmission packet. The inter-packet selective symbol mapper applies a first symbol map pattern to the bit segment based on the transmission iteration of the bit segment and applies a second symbol map pattern to another bit segment of the retransmission packet based on the transmission iteration of the other bit segment. The first symbol map pattern is different from the second symbol map pattern.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: January 3, 2012
    Assignee: Intel Corporation
    Inventors: Vladislav A Chernyshev, Andrey Efimov, Mikhail Lyakh
  • Patent number: 7925964
    Abstract: Described herein are one or more implementations of a high-throughput and memory-efficient “windowed” bidirectional Soft Output Viterbi Algorithm (BI-SOVA) decoder. The described BI-SOVA decoder uses the “window” technique to concurrently decode several different non-overlapping portions of a subject signal in parallel.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: April 12, 2011
    Assignee: Intel Corporation
    Inventors: Andrey Efimov, Andrey V Belogolovy, Vladislav A Chernyshev
  • Patent number: 7836383
    Abstract: An embodiment of a decoder comprises processing elements operating on associative processing. The processing elements may comprise a logic and memory element. Each row of the decoder comprises one or more associative processing elements controlled by a row control element to determine the two minimum values. Each column comprises one or more associative processing elements, an input processing element, and a column control element to determine hard decision bits. The usage of processing elements to construct a decoder may reduce the gate count and decrease the interconnects used to couple the elements.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: November 16, 2010
    Assignee: Intel Corporation
    Inventors: Andrey Efimov, Andrey Belogolovy, Aliaksei Chapyzhenka
  • Publication number: 20100146360
    Abstract: A unified decoder (10) is capable of decoding data encoded with convolutional codes, Turbo codes and LDPC codes. The decoder comprises a first set (20, . . . ,44) and a second set (26, . . . ,30) of trellis processors for calculating path metrics during decoding of convolutional codes and for calculating alpha and beta metrics during decoding of turbo and LDPC codes. The decoder further comprises a normalization unit for the normalization of metrics (46), a set of reliability calculators, a trace back unit (32) and two alpha-beta swap units (38,40) for the redistribution of the metrics to the trellis processors. In at least one embodiment, a unified decoder is implemented within a multi-standard wireless device.
    Type: Application
    Filed: June 14, 2007
    Publication date: June 10, 2010
    Applicant: INTEL CORPORATION
    Inventors: Alexey Trofimenko, Andrey Efimov, Andrey V. Belogolovy, Vladislav A. Chernyshev
  • Patent number: 7685503
    Abstract: A technique to perform fast decoding of a Reed-Solomon code. A first multiplier unit multiplies a matrix Bh with a column vector v using common adders to produce a column vector v1. The vector v represents one of an error locator polynomial, an error evaluator polynomial, and a derivative polynomial for a (n, k) Reed-Solomon code. The matrix Bh is over GF(2) including first h columns of a matrix B. A second multiplier unit multiplies non-unity components of a column vector A with non-zero components of the column vector v1 component-wise in GF(q) to produce a column vector v2, q being equal to n+1. A third multiplier unit multiplies diagonal sub-matrices of a matrix C with corresponding components of the column vector v2 in GF(2) to produce a column vector v3.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: March 23, 2010
    Assignee: Intel Corporation
    Inventors: Andrei Ovchinnikov, Evguenii Krouk, Andrey Efimov, Andrey Belogolovy