Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart fin structures in a semiconductor substrate, wherein the fin structures define a portion of an alignment/overlay mark trench where at least a portion of an alignment/overlay mark will be formed, forming at least one layer of insulating material that overfills the alignment/overlay mark trench and removing excess portions of the layer of insulating material positioned above an upper surface of the plurality of fins to thereby define at least a portion of the alignment/overlay mark positioned within the alignment/overlay mark trench. A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to partially define an alignment/overlay mark trench, an alignment/overlay mark consisting only of at least one insulating material positioned within the alignment/overlay mark trench, and a plurality of FinFET semiconductor devices formed in and above the substrate.

Abstract: In one example, the method disclosed herein includes forming a shared sacrificial gate structure above at least one first fin for a first type of FinFET device and at least one second fin for a second type of FinFET device, wherein the second type is opposite to the first type, and forming a first sidewall spacer around an entire perimeter of the sacrificial gate structure in a single process operation.

Abstract: A method for fabricating a multiple-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure and etching the first workfunction material layer so as to completely remove the first workfunction material layer from all but a first trench of the plurality of trenches. Further, the method includes depositing a second workfunction material in a layer in the plurality of trenches and etching the second workfunction material layer so as to completely remove the second workfunction material layer from all but a second trench of the plurality of trenches. Still further, the method includes depositing a third workfunction material in a layer in the plurality of trenches.

Abstract: One method includes forming a plurality of trenches in a semiconducting substrate to define a plurality of fins, forming a layer of overfill material that overfills the trenches, wherein an upper surface of the overfill material is positioned above an upper surface of the fins, forming a masking layer above the layer of overfill material, wherein the masking layer has an opening that is positioned above a subset of the plurality of fins that is desired to be removed and wherein the subset of fins is comprised of at least one but less than all of the fins, performing an etching process through the masking layer to remove at least a portion of the layer of overfill material and expose the upper surface of the subset of fins, and performing a second etching process on the exposed surface of the subset of fins to remove the subset of fins.

Abstract: One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.

Abstract: A method is provided for forming an integrated circuit having a diode. The method includes forming at least one fin in a shallow trench isolation (STI) oxide layer disposed above a substrate layer. The at least one fin extends from a bottom end adjacent the substrate layer to a top end. The method further includes adding a cathode implant in a first region of the at least one fin and the substrate layer and adding an anode implant in a second region of the at least one fin and the substrate layer such that a junction is formed in the substrate layer below the at least one fin. The method also includes etching away a portion of the STI oxide layer to expose the top end of the at least one fin.

Abstract: Semiconductor devices are formed with a gate last, high-K/metal gate process with complete removal of the polysilicon dummy gate and with a gap having a low aspect ratio for the metal fill. Embodiments include forming a dummy gate electrode on a substrate, the dummy gate electrode having a nitride cap, forming spacers adjacent opposite sides of the dummy gate electrode forming a gate trench therebetween, dry etching the nitride cap, tapering the gate trench top corners; performing a selective dry etch on a portion of the dummy gate electrode, and wet etching the remainder of the dummy gate electrode.

Abstract: A method for fabricating a dual-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure, depositing a low-resistance material layer over the first workfunction material layer, and etching the low-resistance material layer and the first workfunction material layer from a portion of the FinFET structure. The method further includes depositing a second workfunction material in a layer in a plurality of trenches of the portion and depositing a stress material layer over the second workfunction material layer.

Abstract: A method for fabricating a multiple-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure and etching the first workfunction material layer so as to completely remove the first workfunction material layer from all but a first trench of the plurality of trenches. Further, the method includes depositing a second workfunction material in a layer in the plurality of trenches and etching the second workfunction material layer so as to completely remove the second workfunction material layer from all but a second trench of the plurality of trenches. Still further, the method includes depositing a third workfunction material in a layer in the plurality of trenches.

Abstract: Embodiments of the invention provide approaches for replacement metal gate (RMG) diffusion break formation. Specifically, a diffusion break is created after source/drain (S/D) formation, thereby allowing facet free and high quality S/D formation. A dummy gate body is removed selective to a sidewall section of a capping layer and a GOx layer formed over a substrate, and the opening is then extended through the GOx layer and into the substrate by etching the dummy gate body selective to the sidewall section of the capping layer. Retaining the capping layer during the dummy gate body etch enables the diffusion break to be self-aligned to the gate and eliminates device variability due to S/D volume variations. Processing then continues with RMG poly open chemical mechanical planarization (POC) and poly open planarization (POP).

Abstract: Semiconductor devices and methods for fabricating semiconductor devices are provided. In an embodiment, a method for fabricating a semiconductor device includes forming on a semiconductor surface a temporary gate structure including a polysilicon gate and a cap. A spacer is formed around the temporary gate structure. The cap and a portion of the spacer are removed. A uniform liner is deposited overlying the polysilicon gate. The method removes a portion of the uniform liner overlying the polysilicon gate and the polysilicon gate to form a gate trench. Then, a replacement metal gate is formed in the gate trench.

Abstract: Methods are provided for fabricating FinFET integrated circuits on bulk semiconductor substrates. In accordance with one embodiment a patterned hard mask that defines locations of a regular array of a plurality of fins is formed overlying a semiconductor substrate. Portions of the patterned hard mask are removed using a cut mask to form a modified hard mask. The substrate is etched using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches. Selected ones of the plurality of fins are at least partially removed to form isolation regions and an insulating material is deposited to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins.

Abstract: Methods are provided for fabricating FinFET integrated circuits on bulk semiconductor substrates. In accordance with one embodiment a patterned hard mask that defines locations of a regular array of a plurality of fins is formed overlying a semiconductor substrate. Portions of the patterned hard mask are removed using a cut mask to form a modified hard mask. The substrate is etched using the modified hard mask as an etch mask to form a plurality of fins extending upwardly from the substrate and separated by trenches. Selected ones of the plurality of fins are at least partially removed to form isolation regions and an insulating material is deposited to fill the trenches and to cover the at least partially removed selected ones of the plurality of fins.

Abstract: Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.

Abstract: Semiconductor devices are formed with a gate last, high-K/metal gate process with complete removal of the polysilicon dummy gate and with a gap having a low aspect ratio for the metal fill. Embodiments include forming a dummy gate electrode on a substrate, the dummy gate electrode having a nitride cap, forming spacers adjacent opposite sides of the dummy gate electrode forming a gate trench therebetween, dry etching the nitride cap, tapering the gate trench top corners; performing a selective dry etch on a portion of the dummy gate electrode, and wet etching the remainder of the dummy gate electrode.

Abstract: Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.

Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a reduced threshold voltage (Vt) may be achieved in HK/MG transistor elements that are manufactured based on replacement gate electrode integrations. One illustrative method disclosed herein includes forming a first metal gate electrode material layer above a gate dielectric material layer having a dielectric constant of approximately 10 or greater. The method further includes exposing the first metal gate electrode material layer to an oxygen diffusion process, forming a second metal gate electrode material layer above the first metal gate electrode material layer, and adjusting an oxygen concentration gradient and a nitrogen concentration gradient in at least the first metal gate electrode material layer and the gate dielectric material layer.

Abstract: Methods for fabricating stressed MOS devices are provided. In one embodiment, the method comprises providing a silicon substrate having a P-well region and depositing a polycrystalline silicon gate electrode layer overlying the P-well region. P-type dopant ions are implanted into the polycrystalline silicon gate electrode layer to form a P-type implanted region and a first polycrystalline silicon gate electrode is formed overlying the P-well region. Recesses are etched into the P-well region using the first polycrystalline silicon gate electrode as an etch mask. The step of etching is performed by exposing the silicon substrate to tetramethylammonium hydroxide. A tensile stress-inducing material is formed within the recesses.

Abstract: Methods for fabricating stressed MOS devices are provided. In one embodiment, the method comprises providing a silicon substrate having a P-well region and depositing a polycrystalline silicon gate electrode layer overlying the P-well region. P-type dopant ions are implanted into the polycrystalline silicon gate electrode layer to form a P-type implanted region and a first polycrystalline silicon gate electrode is formed overlying the P-well region. Recesses are etched into the P-well region using the first polycrystalline silicon gate electrode as an etch mask. The step of etching is performed by exposing the silicon substrate to tetramethylammonium hydroxide. A tensile stress-inducing material is formed within the recesses.

Abstract: In one illustrative embodiment, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, and forming a plurality of dielectric regions in the bulk substrate after the gate electrode is formed, the dielectric regions being self-aligned with respect to the gate electrode, the dielectric regions having a dielectric constant that is less than a dielectric constant of the bulk substrate.