Abstract: In one embodiment, an apparatus includes a connector for directly connecting the apparatus to a host when the apparatus is received at a host interface configured for receiving a pluggable transceiver, a sampler module configured for under-sampling a periodic waveform transmitted from the host, and an interface for transmitting sampled data to a processing device operable to process and analyze the sampled data for use in determining if the host is operating within specified limits.

Abstract: In one embodiment, an apparatus includes a connector for directly connecting the apparatus to a host when the apparatus is received at a host interface configured for receiving a pluggable transceiver, a sampler module configured for under-sampling a periodic waveform transmitted from the host, and an interface for transmitting sampled data to a processing device operable to process and analyze the sampled data for use in determining if the host is operating within specified limits.

Abstract: Systems and methods for controlling isochronous data streams are disclosed. Particular aspects of the present disclosure are designed to be used with almost any isochronous data stream, but are well-suited for use with the Universal Serial Bus (USB) protocol. Further, aspects of the present disclosure are flexible to accommodate existing configuration possibilities within the USB protocol as well as accommodate proposed future changes in the USB protocol. The flexibility of the systems and methods is provided by calculating: (1) drift between a USB host system time and the application and (2) drift between the USB host system and a USB device clock. Based on these two drift calculations, a time stamp may be synthesized to program a next delivery schedule. Using this time stamp, jitter correction can take place and uniformly-sized packets may be assembled to pass to an application processor.

Abstract: Methods, systems, and devices are described for media synchronization. Multi-stream media processes may include media streams captured with respect to different clock rates. Multi-processor implementations may involve separate clocks associated with different media streams, such as audio and video, respectively. The separate clocks may tend to drift from one another, becoming further out of sync as time passes. Selecting a reference time of one of the processors to function as a “wall clock,” recording frame capture times with respect to the reference time, accounting for propagation delays, and transmitting frame capture times in terms of the reference time may aid in AV synchronization at a device where audio and video streams are received.

Abstract: Methods, systems, and devices are described for media synchronization. Multi-stream media processes may include media streams captured with respect to different clock rates. Multi-processor implementations may involve separate clocks associated with different media streams, such as audio and video, respectively. The separate clocks may tend to drift from one another, becoming further out of sync as time passes. Selecting a reference time of one of the processors to function as a “wall clock,” recording frame capture times with respect to the reference time, accounting for propagation delays, and transmitting frame capture times in terms of the reference time may aid in AV synchronization at a device where audio and video streams are received.

Abstract: An electric plug includes an end block and a power cord. The end block includes a plurality of first connectors and the power cord includes a plurality of second connectors which correspond to the first connectors and detachably connected thereto. The first connectors and second connectors are electrically conductive. One or more first connectors are connected to the second connectors by press-fitting and are retained therewith by friction. Alternatively, the first connectors may be a terminal screw assembly and the second connectors are wires of the power cord.

Abstract: Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.

Abstract: An electric plug includes an end block and a power cord. The end block includes a plurality of first connectors and the power cord includes a plurality of second connectors which correspond to the first connectors and detachably connected thereto. The first connectors and second connectors are electrically conductive. One or more first connectors are connected to the second connectors by press-fitting and are retained therewith by friction. Alternatively, the first connectors may be a terminal screw assembly and the second connectors are wires of the power cord.

Abstract: Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.

Abstract: A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

Abstract: A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

Abstract: A multi-function memory array that includes a DRAM distributed in several DRAM sectors, a Flash EEPROM distributed in several Flash EEPROM sectors, a data bus interconnecting the DRAM sectors and the Flash EEPROM sectors, and a plurality of memory access control circuitries. Each DRAM sector and Flash EEPROM sector can be accessed independently and data can be transferred between a DRAM sector and a Flash EEPROM sector. External data can also be written into either DRAM or Flash EEPROM. Flash EEPROM in one sector is distributed in rows and columns, and cells in each column are separated from the cells in an adjacent column by deep trench isolation regions.

Abstract: A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

Abstract: In a memory cell array, each memory cell includes a control gate disposed laterally adjacent a floating gate. The memory cells in each memory column are disposed inside a single well. The control gate and the floating gate are disposed between two diffusion regions. Each memory cell may be erased and programmed by applying a combination of voltages to the diffusion regions, the control gate, and the well.

Abstract: In a memory cell array, each memory cell includes a control gate disposed laterally adjacent a floating gate. The memory cells in each memory column are disposed inside a single well. The control gate and the floating gate are disposed between two diffusion regions. Each memory cell may be erased and programmed by applying a combination of voltages to the diffusion regions, the control gate, and the well.

Abstract: A memory cell that includes two control gates disposed laterally between two floating gates where each floating gate is capable of holding data. The memory cell is formed by placing a first polysilicon on a substrate of semiconductor material, on which a well is placed. The control gates are preferably formed by a Damascene process, in which a first polysilicon is removed after forming two floating gates, and a second polysilicon is placed between these two floating gates. An anisotropic etching is later done on the second polysilicon to form two control gates.

Abstract: A transfer case for a vehicle that includes a planetary gear assembly, a clutch pack assembly, and a band and drum assembly that provide an overdrive or underdrive and direct drive in combination with a vehicle transmission. In one embodiment, an input shaft drives an outer ring gear of the planetary gear assembly and is coupled to one set of discs of the clutch assembly. A carrier of the planetary gear assembly is coupled to a rear output shaft, where the carrier supports a plurality of pinion gears. A sun gear of the planetary gear assembly is coupled to another set of discs of the clutch assembly that are coupled to the drum. When the clutch assembly is engaged, the ring gear is coupled to the sun gear for direct drive and when the band is engaged, the pinion gears and the ring gear provide underdrive.

Abstract: A memory cell that includes two control gates disposed laterally between two floating gates where each floating gate is capable of holding data. The memory cell is formed by placing a first polysilicon on a substrate of semiconductor material, on which a well is placed. The control gates are preferably formed by a Damascene process, in which a first polysilicon is removed after forming two floating gates, and a second polysilicon is placed between these two floating gates. An anisotropic etching is later done on the second polysilicon to form two control gates.