Abstract: Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.

Abstract: An electric plug includes an end block and a power cord. The end block includes a plurality of first connectors and the power cord includes a plurality of second connectors which correspond to the first connectors and detachably connected thereto. The first connectors and second connectors are electrically conductive. One or more first connectors are connected to the second connectors by press-fitting and are retained therewith by friction. Alternatively, the first connectors may be a terminal screw assembly and the second connectors are wires of the power cord.

Abstract: Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.

Abstract: A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

Abstract: A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

Abstract: A multi-function memory array that includes a DRAM distributed in several DRAM sectors, a Flash EEPROM distributed in several Flash EEPROM sectors, a data bus interconnecting the DRAM sectors and the Flash EEPROM sectors, and a plurality of memory access control circuitries. Each DRAM sector and Flash EEPROM sector can be accessed independently and data can be transferred between a DRAM sector and a Flash EEPROM sector. External data can also be written into either DRAM or Flash EEPROM. Flash EEPROM in one sector is distributed in rows and columns, and cells in each column are separated from the cells in an adjacent column by deep trench isolation regions.

Abstract: A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

Abstract: In a memory cell array, each memory cell includes a control gate disposed laterally adjacent a floating gate. The memory cells in each memory column are disposed inside a single well. The control gate and the floating gate are disposed between two diffusion regions. Each memory cell may be erased and programmed by applying a combination of voltages to the diffusion regions, the control gate, and the well.

Abstract: In a memory cell array, each memory cell includes a control gate disposed laterally adjacent a floating gate. The memory cells in each memory column are disposed inside a single well. The control gate and the floating gate are disposed between two diffusion regions. Each memory cell may be erased and programmed by applying a combination of voltages to the diffusion regions, the control gate, and the well.

Abstract: A memory cell that includes two control gates disposed laterally between two floating gates where each floating gate is capable of holding data. The memory cell is formed by placing a first polysilicon on a substrate of semiconductor material, on which a well is placed. The control gates are preferably formed by a Damascene process, in which a first polysilicon is removed after forming two floating gates, and a second polysilicon is placed between these two floating gates. An anisotropic etching is later done on the second polysilicon to form two control gates.

Abstract: A transfer case for a vehicle that includes a planetary gear assembly, a clutch pack assembly, and a band and drum assembly that provide an overdrive or underdrive and direct drive in combination with a vehicle transmission. In one embodiment, an input shaft drives an outer ring gear of the planetary gear assembly and is coupled to one set of discs of the clutch assembly. A carrier of the planetary gear assembly is coupled to a rear output shaft, where the carrier supports a plurality of pinion gears. A sun gear of the planetary gear assembly is coupled to another set of discs of the clutch assembly that are coupled to the drum. When the clutch assembly is engaged, the ring gear is coupled to the sun gear for direct drive and when the band is engaged, the pinion gears and the ring gear provide underdrive.

Abstract: A memory cell that includes two control gates disposed laterally between two floating gates where each floating gate is capable of holding data. The memory cell is formed by placing a first polysilicon on a substrate of semiconductor material, on which a well is placed. The control gates are preferably formed by a Damascene process, in which a first polysilicon is removed after forming two floating gates, and a second polysilicon is placed between these two floating gates. An anisotropic etching is later done on the second polysilicon to form two control gates.

Abstract: A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

Abstract: A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

Abstract: A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

Abstract: An electrohydraulic clutch includes a bi-directional electric motor, a hydraulic circuit and a multiple plate friction clutch pack. The bi-directional electric motor drives a ball screw through a gear reduction assembly. The ball screw output translates a master piston of the hydraulic circuit which in turn advances and retracts an annular sleeve piston disposed adjacent the friction clutch pack. Hence, actuation of the electric motor displaces hydraulic fluid and compresses or relaxes the friction clutch pack, thereby transferring or inhibiting torque.

Abstract: A transfer case for a vehicle that includes a planetary gear assembly, a clutch pack assembly, and a band and drum assembly that provide an overdrive or underdrive and direct drive in combination with a vehicle transmission. In one embodiment, an input shaft drives an outer ring gear of the planetary gear assembly and is coupled to one set of discs of the clutch assembly. A carrier of the planetary gear assembly is coupled to a rear output shaft, where the carrier supports a plurality of pinion gears. A sun gear of the planetary gear assembly is coupled to another set of discs of the clutch assembly that are coupled to the drum. When the clutch assembly is engaged, the ring gear is coupled to the sun gear for direct drive and when the band is engaged, the pinion gears and the ring gear provide underdrive.

Abstract: An improved game controller. D-pad keys are positioned above a printed circuit board-with plungers guided by housing apertures. The D-pad key is top-loaded into contact with the housing to simplify manufacture and operating reliability. The D-pad key can be depressed downwardly until it contacts a pivot supported by a pivot post. The combination of elements permits significant design flexibility in the orientation and shape and operation of a D-pad key. Front mounted triggers replace front mounted buttons attached to a separate vertical printed circuit board. The triggers function with the main printed circuit board, thereby reducing cost and enhancing product reliability.

Abstract: An ink cartridge selection control mechanism of a multi-ink cartridge writing apparatus, including a plurality of slides fixed to the ink cartridges which are slidably moved in a respective sliding slot on the barrel of the pen. A plurality of springs are mounted around the ink cartridges between the slides and a locating block inside the barrel of the pen. When one ink cartridge is moved by one slide to the extended position for writing, the rounded end of the respective slide is forced into engagement with an expanded, tapered hole at one end of the respective sliding slot to lock the respective ink cartridge in the extended position. When a second ink cartridge is moved toward the extended position, the slide of the extended ink cartridge is forced outwardly to release the extended cartridge from the locked position.