Abstract: A one-coil multi-core inductor-capacitor (LC) oscillator is provided. The one-coil multi-core LC oscillator includes a main coil and at least one mode suppression device. The main coil includes an outer wire and a central wire, wherein the outer wire is coupled to a first core circuit and a second core circuit, and the central wire is coupled between a first node and a second node of the outer wire. More particularly, an outer loop formed by the outer wire corresponds to a first mode of the one-coil multi-core LC oscillator, and inner loops formed by the outer wire and the central wire correspond to a second mode of the one-coil multi-core LC oscillator, where the at least one mode suppression device is configured to suppress one of the first mode and the second mode.

Abstract: A semiconductor device includes a metal layer, a ground plane formed on the metal layer, a first inductor formed on the metal layer, and a first isolation region formed on the metal layer and arranged to separate the first inductor from the ground plane. The first isolation region includes a first main area surrounding the first inductor, and at least one first slot extended from the first main area.

Abstract: A one-coil multi-core inductor-capacitor (LC) oscillator is provided. The one-coil multi-core LC oscillator includes a main coil and at least one mode suppression device. The main coil includes an outer wire and a central wire, wherein the outer wire is coupled to a first core circuit and a second core circuit, and the central wire is coupled between a first node and a second node of the outer wire. More particularly, an outer loop formed by the outer wire corresponds to a first mode of the one-coil multi-core LC oscillator, and inner loops formed by the outer wire and the central wire correspond to a second mode of the one-coil multi-core LC oscillator, where the at least one mode suppression device is configured to suppress one of the first mode and the second mode.

Abstract: A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.

Abstract: A voltage regulator provides a load device with a regulated voltage, and includes a first regulator circuit, a second regulator circuit, a first control loop circuit, and a second control loop circuit. The load device and the first regulator circuit are connected in series. The load device and the second regulator circuit are connected in parallel. The first control loop circuit adaptively adjusts a first bias voltage of the first regulator circuit in response to a load condition at the output node of the voltage regulator, wherein the first control loop circuit includes a capacitor coupled between the first power rail and an output node of a feedback amplifier. The second control loop circuit adaptively adjusts a second bias voltage of the second regulator circuit in response to the load condition at the output node of the voltage regulator.

Abstract: A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.

Abstract: A phase-locked loop (PLL) circuit is provided in the invention. The PLL circuit includes a first DTC, a first selection circuit, and a second selection circuit. The first DTC receives a first delay control signal to dither a reference signal or a feedback signal. The first selection circuit is coupled to the first DTC. The first selection circuit receives the reference signal and the feedback signal, and according to the selection signal, transmits the reference signal or the feedback signal to the first DTC. The second selection circuit is coupled to the first DTC and the first selection circuit. The second selection circuit determines the output paths of an output reference signal or an output feedback signal according to the selection signal.

Abstract: A phase-locked loop (PLL) circuit is provided in the invention. The PLL circuit includes a first DTC, a first selection circuit, and a second selection circuit. The first DTC receives a first delay control signal to dither a reference signal or a feedback signal. The first selection circuit is coupled to the first DTC. The first selection circuit receives the reference signal and the feedback signal, and according to the selection signal, transmits the reference signal or the feedback signal to the first DTC. The second selection circuit is coupled to the first DTC and the first selection circuit. The second selection circuit determines the output paths of an output reference signal or an output feedback signal according to the selection signal.

Abstract: An inductor-capacitor (LC) oscillator with an embedded second harmonic filter and an associated dual core oscillator are provided. The LC oscillator includes a first transistor, a second transistor, a first part-one inductor, a second part-one inductor, a part-one capacitor, a part-two inductor and at least one part-two capacitor. A first end of the first part-one inductor and a first end of the second part-one inductor are coupled to gate terminals of the second transistor and the first transistor, respectively. The part-one capacitor is coupled between the first end of the first part-one inductor and the first end of the second part-one inductor. The part-two inductor is coupled between a second end of the first part-one inductor and a second end of the second part-one inductor. The at least one part-two capacitor is coupled to drain terminals of the first transistor and the second transistor.

Abstract: An inductor-capacitor (LC) oscillator with an embedded second harmonic filter and an associated dual core oscillator are provided. The LC oscillator includes a first transistor, a second transistor, a first part-one inductor, a second part-one inductor, a part-one capacitor, a part-two inductor and at least one part-two capacitor. A first end of the first part-one inductor and a first end of the second part-one inductor are coupled to gate terminals of the second transistor and the first transistor, respectively. The part-one capacitor is coupled between the first end of the first part-one inductor and the first end of the second part-one inductor. The part-two inductor is coupled between a second end of the first part-one inductor and a second end of the second part-one inductor. The at least one part-two capacitor is coupled to drain terminals of the first transistor and the second transistor.

Abstract: A voltage controlled oscillator includes a first inductor, a second inductor, a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, and an inductor-capacitor (LC) tank circuit. A first end of the first inductor and a first end of the second inductor are coupled to a first power rail. A drain node of the first MOS transistor is coupled to a second end of the first inductor. A drain node of the second MOS transistor is coupled to a second end of the second inductor. Source nodes of the first MOS transistor and the second MOS transistor are coupled to a second power rail. The LC tank circuit is coupled to gate nodes of the first MOS transistor and the second MOS transistor, wherein energy is magnetically pumped into the LC tank circuit through the first inductor and the second inductor.

Abstract: A voltage controlled oscillator includes a first inductor, a second inductor, a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, and an inductor-capacitor (LC) tank circuit. A first end of the first inductor and a first end of the second inductor are coupled to a first power rail. A drain node of the first MOS transistor is coupled to a second end of the first inductor. A drain node of the second MOS transistor is coupled to a second end of the second inductor. Source nodes of the first MOS transistor and the second MOS transistor are coupled to a second power rail. The LC tank circuit is coupled to gate nodes of the first MOS transistor and the second MOS transistor, wherein energy is magnetically pumped into the LC tank circuit through the first inductor and the second inductor.

Abstract: A voltage regulator provides a load device with a regulated voltage, and includes a first regulator circuit, a second regulator circuit, a first control loop circuit, and a second control loop circuit. The load device and the first regulator circuit are connected in series. The load device and the second regulator circuit are connected in parallel. The first control loop circuit adaptively adjusts a first bias voltage of the first regulator circuit in response to a load condition at the output node of the voltage regulator, wherein the first control loop circuit includes a capacitor coupled between the first power rail and an output node of a feedback amplifier. The second control loop circuit adaptively adjusts a second bias voltage of the second regulator circuit in response to the load condition at the output node of the voltage regulator.

Abstract: An oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors and two N-type transistors. Source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively. Source electrodes of the two N-type transistors are coupled to a supply voltage, gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively. In addition, the drain electrodes of the two N-type transistors are coupled to two internal nodes of the inductor.

Abstract: A time-to-digital system and associated frequency synthesizer are provided. The time-to-digital system receives a reference clock and a variable clock. The time-to-digital system includes a supplement circuit and a time-to-digital converter (TDC). The supplement circuit generates a delayed reference clock signal and at least one pulse of a variable clock ahead of a transition of the delayed reference clock signal. The delayed reference clock signal is generated according to a delay control signal and the reference clock signal. The delay control signal is determined in response to transitions of the variable clock, and frequency of the variable clock is significantly higher than frequency of the reference clock signal. Being coupled to the supplement circuit, the TDC receives the delayed reference clock signal and the at least one pulse of the variable clock and accordingly produces a TDC signal.

Abstract: A frequency-generating circuit includes a frequency synthesizer circuit and a controller. The frequency synthesizer circuit generates a radio-frequency clock signal according to a reference clock signal and a channel number. The controller is coupled to the frequency synthesizer circuit, generates a power-down control signal for controlling at least a portion of the frequency synthesizer circuit to power down. The frequency synthesizer circuit includes an accumulator for generating an accumulated value according to the channel number. The frequency synthesizer circuit generates the radio-frequency clock signal according to the reference clock signal and the accumulated value. The controller maintains the accumulated value of the accumulator when the portion of the frequency synthesizer circuit powers down.

Abstract: An inductor capacitor (LC) tank includes a first inductor and a first tunable capacitive array. The first inductor has a first terminal and a second terminal, and the first tunable capacitive array has a first terminal and a second terminal. The first tunable capacitive array is at a path branching from a first point between the first terminal and the second terminal of the first inductor, the first terminal of the first tunable capacitive array is coupled to the first point, and the second terminal of the first tunable capacitive array and the second terminal of the first inductor are coupled to a reference voltage.

Abstract: An oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors and two N-type transistors. Source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively. Source electrodes of the two N-type transistors are coupled to a supply voltage, gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively. In addition, the drain electrodes of the two N-type transistors are coupled to two internal nodes of the inductor.

Abstract: A time-to-digital system and associated frequency synthesizer are provided. The time-to-digital system receives a reference clock and a variable clock. The time-to-digital system includes a supplement circuit and a time-to-digital converter (TDC). The supplement circuit generates a delayed reference clock signal and at least one pulse of a variable clock ahead of a transition of the delayed reference clock signal. The delayed reference clock signal is generated according to a delay control signal and the reference clock signal. The delay control signal is determined in response to transitions of the variable clock, and frequency of the variable clock is significantly higher than frequency of the reference clock signal. Being coupled to the supplement circuit, the TDC receives the delayed reference clock signal and the at least one pulse of the variable clock and accordingly produces a TDC signal.

Abstract: An inductor capacitor (LC) tank includes a first inductor and a first tunable capacitive array. The first inductor has a first terminal and a second terminal, and the first tunable capacitive array has a first terminal and a second terminal. The first tunable capacitive array is at a path branching from a first point between the first terminal and the second terminal of the first inductor, the first terminal of the first tunable capacitive array is coupled to the first point, and the second terminal of the first tunable capacitive array and the second terminal of the first inductor are coupled to a reference voltage.