Patents by Inventor Ang-Sheng Lin
Ang-Sheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160336914Abstract: An inductor capacitor (LC) tank includes a first inductor and a first tunable capacitive array. The first inductor has a first terminal and a second terminal, and the first tunable capacitive array has a first terminal and a second terminal. The first tunable capacitive array is at a path branching from a first point between the first terminal and the second terminal of the first inductor, the first terminal of the first tunable capacitive array is coupled to the first point, and the second terminal of the first tunable capacitive array and the second terminal of the first inductor are coupled to a reference voltage.Type: ApplicationFiled: February 22, 2016Publication date: November 17, 2016Inventors: Kun-Yin Wang, Wei-Hao Chiu, Ang-Sheng Lin
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Patent number: 9473147Abstract: A frequency dividing apparatus includes: a plurality of latching devices arranged to selectively generate an output signal having a first oscillating frequency or a second oscillating frequency different from the first oscillating frequency according to an input clock signal and a first reset signal; and a controlling device arranged to generate the first reset signal at least according to a programming input signal; wherein the first reset signal is arranged to reset a first latching device in the plurality of latching devices to make the plurality of latching devices to generate the output signal having the second oscillating frequency.Type: GrantFiled: March 3, 2015Date of Patent: October 18, 2016Assignee: MEDIATEK INC.Inventors: Wei-Hao Chiu, Ang-Sheng Lin, Kun-Yin Wang
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Publication number: 20160261273Abstract: A frequency dividing apparatus includes: a plurality of latching devices arranged to selectively generate an output signal having a first oscillating frequency or a second oscillating frequency different from the first oscillating frequency according to an input clock signal and a first reset signal; and a controlling device arranged to generate the first reset signal at least according to a programming input signal; wherein the first reset signal is arranged to reset a first latching device in the plurality of latching devices to make the plurality of latching devices to generate the output signal having the second oscillating frequency.Type: ApplicationFiled: March 3, 2015Publication date: September 8, 2016Inventors: Wei-Hao Chiu, Ang-Sheng Lin, Kun-Yin Wang
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Patent number: 9397557Abstract: A charge pump at least includes a current source, a first switch, a second switch, a level-shift circuit, and a capacitor. The first switch is coupled between the current source and an internal node. The capacitor is coupled between the internal node and the level-shift circuit. The second switch is coupled between the internal node and an output node. The first switch performs a closing-and-opening operation and the level-shift circuit performs a level-shift operation while the second switch is kept open and the internal node is isolated from the output node. The operating range of the charge pump is effectively widened by using the proposed design.Type: GrantFiled: May 15, 2014Date of Patent: July 19, 2016Assignee: MEDIATEK INC.Inventors: Wei-Hao Chiu, Ang-Sheng Lin
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Patent number: 9331569Abstract: A current generating circuit, which comprises: a first capacitor, comprising a first terminal and a second terminal; a second capacitor, comprising a first terminal and a second terminal; a first charge adjusting path, arranged for adjusting charges of the first capacitor according to a first charge adjusting voltage; a second charge adjusting path, arranged for adjusting charges of the second capacitor according to the first charge adjusting voltage; and a current generating path, coupled to the first capacitor and the second capacitor, arranged for generating a target current based on a difference between a first voltage provided by the first capacitor and a second voltage provided by the second capacitor.Type: GrantFiled: January 14, 2015Date of Patent: May 3, 2016Assignee: MEDIATEK INC.Inventors: Wei-Hao Chiu, Ang-Sheng Lin
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Patent number: 9298199Abstract: A voltage generating circuit comprising: an output current generating circuit, generating an output current, such that an output voltage is generated at an output terminal, according to an output voltage control signal; a comparing device, comprising a first input terminal receiving a reference voltage, a second input terminal receiving a feedback voltage related with the output voltage, and an output terminal outputting the output voltage control signal according to the reference voltage and the feedback voltage; an adjustable voltage dropping circuit, comprising a first terminal coupled to the second input terminal, and a second terminal coupled to the output terminal; and a current source, for generating a predetermined current to the first terminal of the adjustable voltage dropping circuit, thereby the feedback voltage is generated at the first terminal of the adjustable voltage dropping circuit. The predetermined current flows through the adjustable voltage dropping circuit to the output terminal.Type: GrantFiled: August 13, 2014Date of Patent: March 29, 2016Assignee: MEDIATEK INC.Inventors: Wei-Hao Chiu, Kun-Yin Wang, Ang-Sheng Lin
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Publication number: 20160048145Abstract: A voltage generating circuit comprising: an output current generating circuit, generating an output current, such that an output voltage is generated at an output terminal, according to an output voltage control signal; a comparing device, comprising a first input terminal receiving a reference voltage, a second input terminal receiving a feedback voltage related with the output voltage, and an output terminal outputting the output voltage control signal according to the reference voltage and the feedback voltage; an adjustable voltage dropping circuit, comprising a first terminal coupled to the second input terminal, and a second terminal coupled to the output terminal; and a current source, for generating a predetermined current to the first terminal of the adjustable voltage dropping circuit, thereby the feedback voltage is generated at the first terminal of the adjustable voltage dropping circuit. The predetermined current flows through the adjustable voltage dropping circuit to the output terminal.Type: ApplicationFiled: August 13, 2014Publication date: February 18, 2016Inventors: Wei-Hao Chiu, Kun-Yin Wang, Ang-Sheng Lin
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Publication number: 20150333623Abstract: A charge pump at least includes a current source, a first switch, a second switch, a level-shift circuit, and a capacitor. The first switch is coupled between the current source and an internal node. The capacitor is coupled between the internal node and the level-shift circuit. The second switch is coupled between the internal node and an output node. The first switch performs a closing-and-opening operation and the level-shift circuit performs a level-shift operation while the second switch is kept open and the internal node is isolated from the output node. The operating range of the charge pump is effectively widened by using the proposed design.Type: ApplicationFiled: May 15, 2014Publication date: November 19, 2015Applicant: MediaTek Inc.Inventors: Wei-Hao CHIU, Ang-Sheng LIN
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Patent number: 8890736Abstract: A signal mixing circuit which mixes input signal(s) and oscillation signal(s) by mixer block(s) to provide a mixed signal. Each mixer block includes a summing node and a circuit unit; the summing node is arranged to provide a sum signal by summing an input signal and an oscillation signal, and the circuit unit is arranged to alternate between a first state and a second state in response to alternating of the oscillation signal; wherein the circuit unit is arranged to provide driving contribution to the mixed signal in response to the sum signal during the first state, and to stop providing driving contribution during the second state. An associated converter, e.g., a digital-to-analog converter, is also disclosed.Type: GrantFiled: March 14, 2013Date of Patent: November 18, 2014Assignee: MEDIATEK Inc.Inventors: Wei-Hao Chiu, Ang-Sheng Lin
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Patent number: 8847662Abstract: A mixer for providing a mixed signal by mixing an input signal and an oscillation signal, comprising a follower and a switch. The follower is arranged to conduct a driving contribution from a bias terminal to an output terminal following a signal at an input terminal, wherein the input terminal and the bias terminal are respectively coupled to the input signal and the oscillation signal, and the output terminal is arranged to output the mixed signal. The switch is arranged to selectively conduct the output terminal to a reference level in response to alternating of the oscillation signal. An associated signal circuit is also disclosed.Type: GrantFiled: March 14, 2013Date of Patent: September 30, 2014Assignee: Mediatek Inc.Inventors: Wei-Hao Chiu, Ang-Sheng Lin
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Patent number: 8831549Abstract: A receiver circuit, e.g., a low-IF receiver, including two mixing paths. The two mixing paths scale an input signal respectively by two mixing gains and shift phase of the input signal respectively by two mixing phase offsets to provide two mixed signals. The two mixing gains and the two mixing phase offsets are arranged to produce an amplitude adjustment between amplitudes of the two mixed signals and a phase difference of 90 degrees plus a phase adjustment between phases of the two mixed signals. With the amplitude adjustment and/or the phase adjustment properly tuned to nonzero value(s) in association with band-pass response of the receiver circuit, image rejection can be achieved and optimized. Associated method is also disclosed.Type: GrantFiled: March 12, 2013Date of Patent: September 9, 2014Assignee: Mediatek Inc.Inventors: Ang-Sheng Lin, Wei-Hao Chiu
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Patent number: 8749280Abstract: A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter arranged to provide a shifted reference clock by changing phase of a frequency reference clock, and a time-to-digital converter (TDC) for producing a digital TDC output by quantizing a time difference between said RF clock and said shifted reference clock; wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.Type: GrantFiled: April 18, 2012Date of Patent: June 10, 2014Assignee: Mediatek Inc.Inventors: Ang-Sheng Lin, Robert Bogdan Staszewski, Yi-Hsien Cho
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Publication number: 20140080437Abstract: A receiver circuit, e.g., a low-IF receiver, including two mixing paths. The two mixing paths scale an input signal respectively by two mixing gains and shift phase of the input signal respectively by two mixing phase offsets to provide two mixed signals. The two mixing gains and the two mixing phase offsets are arranged to produce an amplitude adjustment between amplitudes of the two mixed signals and a phase difference of 90 degrees plus a phase adjustment between phases of the two mixed signals. With the amplitude adjustment and/or the phase adjustment properly tuned to nonzero value(s) in association with band-pass response of the receiver circuit, image rejection can be achieved and optimized. Associated method is also disclosed.Type: ApplicationFiled: March 12, 2013Publication date: March 20, 2014Applicant: MEDIATEK INC.Inventors: Ang-Sheng Lin, Wei-Hao Chiu
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Publication number: 20140070973Abstract: A signal mixing circuit which mixes input signal(s) and oscillation signal(s) by mixer block(s) to provide a mixed signal. Each mixer block includes a summing node and a circuit unit; the summing node is arranged to provide a sum signal by summing an input signal and an oscillation signal, and the circuit unit is arranged to alternate between a first state and a second state in response to alternating of the oscillation signal; wherein the circuit unit is arranged to provide driving contribution to the mixed signal in response to the sum signal during the first state, and to stop providing driving contribution during the second state. An associated converter, e.g., a digital-to-analog converter, is also disclosed.Type: ApplicationFiled: March 14, 2013Publication date: March 13, 2014Applicant: MEDIATEK Inc.Inventors: Wei-Hao Chiu, Ang-Sheng Lin
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Publication number: 20140070866Abstract: A mixer for providing a mixed signal by mixing an input signal and an oscillation signal, comprising a follower and a switch. The follower is arranged to conduct a driving contribution from a bias terminal to an output terminal following a signal at an input terminal, wherein the input terminal and the bias terminal are respectively coupled to the input signal and the oscillation signal, and the output terminal is arranged to output the mixed signal. The switch is arranged to selectively conduct the output terminal to a reference level in response to alternating of the oscillation signal. An associated signal circuit is also disclosed.Type: ApplicationFiled: March 14, 2013Publication date: March 13, 2014Applicant: MEDIATEK Inc.Inventors: Wei-Hao Chiu, Ang-Sheng Lin
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Patent number: 8653862Abstract: A frequency divider includes a phase selection circuit, control circuit and a retiming circuit. The phase selection circuit is arranged to receive a plurality of input signals with different phases, and generate an output signal by selectively outputting one of the input signals according to a plurality of retimed signals. The control circuit is arranged to receive the output signal to generate a plurality of control signals. The retiming circuit is arranged to retime the control signals to generate the retimed signals according to the input signals.Type: GrantFiled: June 13, 2011Date of Patent: February 18, 2014Assignee: Mediatek Inc.Inventor: Ang-Sheng Lin
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Patent number: 8593182Abstract: A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter coupled to said oscillator for providing a shifted RF clock by changing phase of said RF clock, and a time-to-digital converter (TDC) coupled to said phase shifter for quantizing a time difference between a frequency reference clock and said shifted RF clock, wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.Type: GrantFiled: April 18, 2012Date of Patent: November 26, 2013Assignee: Mediatek Inc.Inventors: Ang-Sheng Lin, Robert Bogdan Staszewski, Yi-Hsien Cho
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Publication number: 20130093469Abstract: A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter coupled to said oscillator for providing a shifted RF clock by changing phase of said RF clock, and a time-to-digital converter (TDC) coupled to said phase shifter for quantizing a time difference between a frequency reference clock and said shifted RF clock, wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.Type: ApplicationFiled: April 18, 2012Publication date: April 18, 2013Applicant: MEDIATEK INC.Inventors: Ang-Sheng Lin, Robert Bogdan Staszewski, Yi-Hsien Cho
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Publication number: 20130093470Abstract: A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter arranged to provide a shifted reference clock by changing phase of a frequency reference clock, and a time-to-digital converter (TDC) for producing a digital TDC output by quantizing a time difference between said RF clock and said shifted reference clock; wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.Type: ApplicationFiled: April 18, 2012Publication date: April 18, 2013Applicant: MEDIATEK INC.Inventors: Ang-Sheng Lin, Robert Bogdan Staszewski, Yi-Hsien Cho
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Publication number: 20120313673Abstract: A frequency divider includes a phase selection circuit, control circuit and a retiming circuit. The phase selection circuit is arranged to receive a plurality of input signals with different phases, and generate an output signal by selectively outputting one of the input signals according to a plurality of retimed signals. The control circuit is arranged to receive the output signal to generate a plurality of control signals.Type: ApplicationFiled: June 13, 2011Publication date: December 13, 2012Inventor: Ang-Sheng Lin