Abstract: Described herein is an innovative method smoothing substrate surfaces. The surfaces to be smoothed may be a surface of a patterned feature of the substrate or may be an unpatterned surface of the substrate. The techniques disclosed utilize atomic layer deposition (ALD) techniques to smooth surfaces. For example, the use of ALD to smooth the line edge roughness of a patterned feature or roughness of a surface of an unpatterned layer is described. ALD can grow high quality films with atomic level thickness controllability and conformality. The rough, sharp asperities on patterned features (for example on sidewalls or tops of a patterned feature) or on a surface can be smoothed by precisely growing material layer by layer over the rough surface. Thus, asperities on a surface may be smoothed, improving the manufacturability and/or device performance.

Abstract: Double plug methods for tone inversion patterning are described. In an embodiment, a method may include receiving the substrate having a multi-line layer formed thereon. Such a method may also include forming a patterned recess in the multi-line layer, the recess defining an inversion pattern on the substrate. The methods may also include depositing a first plug layer in the patterned recess using a first deposition process. Additionally, the methods may include depositing a second plug layer in the patterned recess using a second deposition process, the second deposition process being different from the first deposition process.

Abstract: Embodiments of methods and systems for patterning of low aspect ratio stacks are described. In one embodiment, a method may include receiving a substrate comprising a patterned organic planarizing layer (OPL) mask wherein a surface of the OPL mask is exposed, the OPL mask landing on a dielectric layer. The method may also include performing a partial etch of the dielectric layer in a region exposed by the OPL mask. Additionally, the method may include depositing a capping material on a surface of the OPL mask. The method may also include performing a cyclical process of the partial etch of the dielectric layer and deposition of the capping material on a surface of the OPL mask until the dielectric layer is removed to a target depth. In such embodiments, the cyclical process generates an output patterned substrate with a target line edge roughness (LER).

Abstract: A method is provided for self-aligned multi-patterning on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting film-forming modules, etching modules, and transfer modules. A workpiece having a mandrel pattern formed thereon is received into the common manufacturing platform. A sidewall spacer pattern is formed based, at least in part, on the mandrel pattern, the sidewall spacer pattern having a plurality of second features separated by a second pitch distance with the first pitch distance being greater than the second pitch distance. The integrated sequence of processing steps is executed within the common manufacturing platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment.

Abstract: Double plug methods for tone inversion patterning are described. In an embodiment, a method may include receiving the substrate having a multi-line layer formed thereon. Such a method may also include forming a patterned recess in the multi-line layer, the recess defining an inversion pattern on the substrate. The methods may also include depositing a first plug layer in the patterned recess using a first deposition process. Additionally, the methods may include depositing a second plug layer in the patterned recess using a second deposition process, the second deposition process being different from the first deposition process.

Abstract: This disclosure relates to a method for using a high volume manufacturing system for processing and measuring workpieces in a semiconductor processing sequence without leaving the system's controlled environment (e.g., sub-atmospheric pressure). The system includes an active interdiction control system to implement corrective processing within the system when a non-conformity is detected. The corrective processing method can include a remedial process sequence to correct the non-conformity or compensate for the non-conformity during subsequent process. The non-conformity may be associated with fabrication measurement data, process parameter data, and/or platform performance data.

Abstract: This disclosure relates to a high volume manufacturing system for processing and measuring workpieces in a semiconductor processing sequence without leaving the system's controlled environment (e.g., sub-atmospheric pressure). The system includes an active interdiction control system to implement corrective processing within the system when a non-conformity is detected. The corrective processing can include a remedial process sequence to correct the non-conformity or compensate for the non-conformity during subsequent process. The non-conformity may be associated with fabrication measurement data, process parameter data, and/or platform performance data.

Abstract: Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.

Abstract: A process is provided in which etched layer(s) are protected from residues or defects caused by or resulting from exposure to atmospheric conditions. Protection is provided through the formation of an encapsulation layer post etch. In one embodiment, the encapsulation is provided by a thin layer formed in an atomic layer deposition (ALD) process. The thin layer prevents the etched layer(s) from exposure to air. This encapsulation process may take place after the etch process thus allowing for substrates to be subsequently exposed to atmospheric conditions with little or no queue time constraints being needed for staging subsequent wet clean processing steps. In one embodiment, the encapsulation process may be performed with no vacuum break between the etch process and the encapsulation process. In one embodiment, the encapsulation film is compatible with subsequent wet process steps and can be removed during this wet process steps without adverse effects.

Abstract: This disclosure relates to a high volume manufacturing system for processing and measuring workpieces in a semiconductor processing sequence without leaving the system's controlled environment (e.g., sub-atmospheric pressure). The systems process chambers are connected to each other via transfer chambers used to move the workpieces, in the controlled environment, between the process chambers. The transfer chambers include a measurement region with dedicated workpiece support chucks capable of translating and/or rotating the workpiece during the measurement.

Abstract: This disclosure relates to a high volume manufacturing system for processing and measuring workpieces in a semiconductor processing sequence without leaving the system's controlled environment (e.g., sub-atmospheric pressure). The systems process chambers are connected to each other via transfer chambers used to move the workpieces, in the controlled environment, between the process chambers. Further, the pass-through chambers may be disposed between the transfer chambers or between the transfer chamber and the process chamber. The pass-through chambers may include a measurement region to measure workpiece attributes when the workpiece is moved through or placed in the pass-through chamber. The transfer chambers may also have separate measurement regions within their internal space to measure other attributes of the workpiece.

Abstract: An atomic layer deposition (ALD) technique is used to deposit one or more layers on hard mask layers and the sidewalls of low-K dielectric trench as part of the trench etch process. The ALD layer(s) can prevent the hard mask from being eroded during various hard mask open processes. Further, the ALD layer(s) may be utilized to prevent the low-K dielectric sidewall from being laterally etched during the low-K dielectric trench etch. Hence, better control of the trench profile and better critical dimension control may be provided.

Abstract: Embodiments of methods and systems for patterning of low aspect ratio stacks are described. In one embodiment, a method may include receiving a substrate comprising a patterned organic planarizing layer (OPL) mask wherein a surface of the OPL mask is exposed, the OPL mask landing on a dielectric layer. The method may also include performing a partial etch of the dielectric layer in a region exposed by the OPL mask. Additionally, the method may include depositing a capping material on a surface of the OPL mask. The method may also include performing a cyclical process of the partial etch of the dielectric layer and deposition of the capping material on a surface of the OPL mask until the dielectric layer is removed to a target depth. In such embodiments, the cyclical process generates an output patterned substrate with a target line edge roughness (LER).

Abstract: A substrate is provided with a patterned layer over a stack of one or more processing layers. The processing layers include at least one patterned layer and one etch target layer. CD trimming between the CD of the patterned layer and the CD of the etch target layer may be achieved after the pattern is transferred to the etch target layer. After the etch target layer is patterned, a plasma free gas phase etch process may be used to trim the CD of the etch target layer to finely tune the CD. In an alternate embodiment, plasma etch trim processes may be used in combination with the gas phase etch process. In such an embodiment, partial CD trimming may be achieved via the plasma etching of the various process layers and then additional CD trimming may be achieved by subjecting the etch target layer to the plasma free gas phase etch after the desired pattern has been formed in the etch target layer.

Abstract: Methods and systems for in-situ spacer reshaping for self-aligned multi-patterning are described. In an embodiment, a method of forming a spacer pattern on a substrate may include providing a substrate with a spacer. The method may also include performing a passivation treatment to form a passivation layer on the spacer. Additionally, the method may include performing spacer reshaping treatment to reshape the spacer. The method may also include controlling the passivation treatment and spacer reshaping treatment in order to achieve spacer formation objectives.

Abstract: A method is provided for self-aligned multi-patterning on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting film-forming modules, etching modules, and transfer modules. A workpiece having a mandrel pattern formed thereon is received into the common manufacturing platform. A sidewall spacer pattern is formed based, at least in part, on the mandrel pattern, the sidewall spacer pattern having a plurality of second features separated by a second pitch distance with the first pitch distance being greater than the second pitch distance. The integrated sequence of processing steps is executed within the common manufacturing platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment.

Abstract: A method is provided for self-aligned multi-patterning on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting one or more film-forming modules, one or more etching modules, and one or more transfer modules. A workpiece having a mandrel pattern formed thereon is received into the common manufacturing platform. A sidewall spacer pattern is formed based, at least in part, on the mandrel pattern, the sidewall spacer pattern having a plurality of second features separated by a second pitch distance with the first pitch distance being greater than the second pitch distance. The integrated sequence of processing steps is executed within the common manufacturing platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment. Broadly, forming a sidewall spacer pattern based on the mandrel pattern.

Abstract: Provided is a method of patterning spacers, the method comprising: providing an initial patterned structure in a substrate in a processing chamber, the initial patterned structure comprising an organic mandrel and an underlying layer; exposing the patterned structure in a direct current superposition (DCS) plasma treatment process, the process depositing a layer of a first material on the initial patterned structure; performing an atomic layer conformal deposition process using a second material, the first material providing protection to the organic mandrel at the beginning of the atomic layer conformal deposition process; performing a spacer etch mandrel pull process, the process creating a final patterned structure with a target final sidewall angle; concurrently controlling integration operating variables in the DCS plasma treatment process, the atomic layer conformal deposition process, and the spacer etch mandrel pull process in order to meet the target final sidewall angle and other integration objecti

Abstract: Embodiments are disclosed for processing microelectronic workpieces having patterned structures to improve mandrel pull from spacers for multi-color patterning. The disclosed embodiments form patterned structures on a substrate including mandrels, form spacers adjacent the mandrels that are recessed such that a height of the spacers is less than the height of the mandrels, form protective caps over the spacers while exposing top surfaces of the mandrels, and remove the mandrels to leave a spacer pattern with cap protection. The remaining spacer pattern can then be transferred to underlying layers in additional process steps. The recessing of the spacers and formation of the protective caps tends to reduce or eliminate spacer damage suffered by prior solutions during mandrel pull from spacers for multi-color patterning.

Abstract: Provided is a method for critical dimension (CD) trimming of a structure pattern in a substrate, the method comprising: providing a substrate in a process chamber of a patterning system, the substrate comprising a first structure pattern and an underlying layer, the underlying layer comprising a silicon anti-reflective coating (SiARC) or a silicon oxynitride (SiON) layer, an optical planarization layer, and a target patterning layer; performing an optional CD trimming process of the first structure pattern; performing a series of processes to open the SiARC or SiON layer and performing additional CD trimming if required; and performing a series of processes to open the optical planarization layer, the series of processes generating a final structure pattern, and performing additional CD trimming if required; wherein the planarization layer is one of a group comprising an advance patterning film (APF), an organic dielectric layer (ODL) or a spin-on hardmask (SOH) layer.