Patents by Inventor Angelo Di Sena
Angelo Di Sena has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9152559Abstract: A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.Type: GrantFiled: November 7, 2014Date of Patent: October 6, 2015Assignee: Micron Technology, Inc.Inventors: Procolo Carannante, Angelo Di Sena, Fabio Salvati, Giuseppe Ferrari, Anna Sorgente
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Patent number: 9146854Abstract: A restoring operation of a storage device based on a flash memory. In an embodiment, a storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A method may detect a plurality of conflicting physical blocks for a corrupted logical block and determines a plurality of validity indexes. One or more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block. At the end, each one of the non-selected conflicting physical blocks is discarded.Type: GrantFiled: October 13, 2011Date of Patent: September 29, 2015Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna
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Publication number: 20150127892Abstract: A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.Type: ApplicationFiled: November 7, 2014Publication date: May 7, 2015Inventors: Procolo Carannante, Angelo Di Sena, Fabio Salvati, Giuseppe Ferrari, Anna Sorgente
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Patent number: 8954649Abstract: A solution for managing a storage device based on a flash memory is proposed. A corresponding method starts with the step for mapping a logical memory space of the storage device (including a plurality of logical blocks) on a physical memory space of the flash memory (including a plurality of physical blocks, which are adapted to be erased individually). The physical blocks include a set of first physical blocks (corresponding to the logical blocks) and a set of second—or spare—physical blocks (for replacing each bad physical block that is unusable). The method continues by detecting each bad physical block. Each bad physical block is then discarded, so to prevent using the bad physical block for mapping the logical memory space.Type: GrantFiled: August 2, 2011Date of Patent: February 10, 2015Assignee: SK Hynix Inc.Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna
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Patent number: 8924638Abstract: A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.Type: GrantFiled: April 5, 2013Date of Patent: December 30, 2014Assignee: Micron Technology, Inc.Inventors: Procolo Carannante, Angelo Di Sena, Fabio Salvati, Giuseppe Ferrari, Anna Sorgente
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Patent number: 8782345Abstract: Subject matter disclosed herein relates to sub-block accessible cache memory.Type: GrantFiled: August 5, 2013Date of Patent: July 15, 2014Assignee: Micron Technology, Inc.Inventors: Giuseppe Ferrari, Procolo Carannante, Angelo Di Sena, Fabio Salvati, Anna Sorgente
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Publication number: 20130326127Abstract: Subject matter disclosed herein relates to sub-block accessible cache memory.Type: ApplicationFiled: August 5, 2013Publication date: December 5, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Giuseppe Ferrari, Pracolo Carannante, Angelo Di Sena, Fabio Salvati, Anna Sorgente
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Patent number: 8516194Abstract: Apparatus and methods for caching data are disclosed. Data is stored in a non-sub-block accessible nonvolatile memory, such as a NAND flash. A portion of the stored data is cached in a cache implemented using phase change memory using a sub-block accessible address.Type: GrantFiled: November 22, 2010Date of Patent: August 20, 2013Assignee: Micron Technology, Inc.Inventors: Giuseppe Ferrari, Procolo Carannante, Angelo Di Sena, Fabio Salvati, Anna Sorgente
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Publication number: 20120304000Abstract: A restoring operation of a storage device based on a flash memory. In an embodiment, a storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A method may detect a plurality of conflicting physical blocks for a corrupted logical block and determines a plurality of validity indexes. One or more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block. At the end, each one of the non-selected conflicting physical blocks is discarded.Type: ApplicationFiled: October 13, 2011Publication date: November 29, 2012Applicants: STMICROELECTRONICS PVT. LTD., STMICROELECTRONICS S.R.L.Inventors: Sudeep BISWAS, Angelo DI SENA, Domenico MANNA
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Publication number: 20120131261Abstract: Subject matter disclosed herein relates to sub-block accessible cache memory.Type: ApplicationFiled: November 22, 2010Publication date: May 24, 2012Applicant: Micron Technology, Inc.Inventors: Giuseppe Ferrari, Procolo Carannante, Angelo Di Sena, Fabio Salvati, Anna Sorgente
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Publication number: 20120117303Abstract: Subject matter disclosed herein relates to storing information via a NAND flash translation layer.Type: ApplicationFiled: November 4, 2010Publication date: May 10, 2012Applicant: Numonyx B.V.Inventors: Procolo Carannante, Angelo Di Sena, Fabio Salvati, Giuseppe Ferrari, Anna Sorgente
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Patent number: 8099545Abstract: A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased.Type: GrantFiled: December 20, 2010Date of Patent: January 17, 2012Assignees: STMicroelectronics S.r.l., STMicroelectronics Pvt. Ltd.Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna
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Publication number: 20110289266Abstract: A solution for managing a storage device based on a flash memory is proposed. A corresponding method starts with the step for mapping a logical memory space of the storage device (including a plurality of logical blocks) on a physical memory space of the flash memory (including a plurality of physical blocks, which are adapted to be erased individually). The physical blocks include a set of first physical blocks (corresponding to the logical blocks) and a set of second—or spare—physical blocks (for replacing each bad physical block that is unusable). The method continues by detecting each bad physical block. Each bad physical block is then discarded, so to prevent using the bad physical block for mapping the logical memory space.Type: ApplicationFiled: August 2, 2011Publication date: November 24, 2011Applicants: STMICROELECTRONICS PVT. LTD., STMICROELECTRONICS S.R.L.Inventors: SUDEEP BISWAS, ANGELO DI SENA, DOMENICO MANNA
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Patent number: 8041883Abstract: A solution for restoring operation of a storage device based on a flash memory is proposed. The storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A corresponding method starts by detecting a plurality of conflicting physical blocks for a corrupted logical block (resulting from a breakdown of the storage device). The method continues by determining a plurality of validity indexes (indicative of the number of last versions of the logical sectors of the corrupted logical block that are stored in the conflicting physical blocks). One ore more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block.Type: GrantFiled: May 9, 2007Date of Patent: October 18, 2011Assignees: STMicroelectronics S.r.l., STMicroelectronics Pvt. Ltd.Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna
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Patent number: 7991942Abstract: A solution for managing a storage device based on a flash memory is proposed. A corresponding method starts with the step for mapping a logical memory space of the storage device (including a plurality of logical blocks) on a physical memory space of the flash memory (including a plurality of physical blocks, which are adapted to be erased individually). The physical blocks include a set of first physical blocks (corresponding to the logical blocks) and a set of second—or spare—physical blocks (for replacing each bad physical block that is unusable). The method continues by detecting each bad physical block. Each bad physical block is then discarded, so to prevent using the bad physical block for mapping the logical memory space.Type: GrantFiled: May 9, 2007Date of Patent: August 2, 2011Assignees: STMicroelectronics S.R.L., STMicroelectronics Pvt. Ltd.Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna
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Publication number: 20110087832Abstract: A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased.Type: ApplicationFiled: December 20, 2010Publication date: April 14, 2011Applicants: STMicroelectronics, S.r.l., STMicroelectronics Pvt. Ltd.Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna
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Patent number: 7882301Abstract: A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased.Type: GrantFiled: May 9, 2007Date of Patent: February 1, 2011Assignees: STMicroelectronics S.r.l., STMIcroelectronics Pvt. Ltd.Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna
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Patent number: 7457909Abstract: A method controls write/erase operations in a memory device, such as a NAND flash memory. The method includes dividing the memory device in physical blocks, wherein each physical block is comprised of a number of pages; considering the memory device as comprising consecutive virtual blocks, each virtual block including consecutive sectors; associating to each virtual block a virtual block number; selecting the size of the virtual blocks equal to a multiple of the size of the physical blocks; and creating a virtual-to-physical mapping table having entries. Each entry in the mapping table stores a pointer to a root node of a tree structure that links logically a set of physical blocks in the memory device.Type: GrantFiled: January 14, 2005Date of Patent: November 25, 2008Inventors: Angelo Di Sena, Agata Intini
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Publication number: 20080282045Abstract: A solution for managing a storage device based on a flash memory is proposed. A corresponding method starts with the step for mapping a logical memory space of the storage device (including a plurality of logical blocks) on a physical memory space of the flash memory (including a plurality of physical blocks, which are adapted to be erased individually). The physical blocks include a set of first physical blocks (corresponding to the logical blocks) and a set of second—or spare—physical blocks (for replacing each bad physical block that is unusable). The method continues by detecting each bad physical block. Each bad physical block is then discarded, so to prevent using the bad physical block for mapping the logical memory space.Type: ApplicationFiled: May 9, 2007Publication date: November 13, 2008Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna
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Publication number: 20080282025Abstract: A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased.Type: ApplicationFiled: May 9, 2007Publication date: November 13, 2008Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna