Patents by Inventor Angelo Di Sena

Angelo Di Sena has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9152559
    Abstract: A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: October 6, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Procolo Carannante, Angelo Di Sena, Fabio Salvati, Giuseppe Ferrari, Anna Sorgente
  • Patent number: 9146854
    Abstract: A restoring operation of a storage device based on a flash memory. In an embodiment, a storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A method may detect a plurality of conflicting physical blocks for a corrupted logical block and determines a plurality of validity indexes. One or more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block. At the end, each one of the non-selected conflicting physical blocks is discarded.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: September 29, 2015
    Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna
  • Publication number: 20150127892
    Abstract: A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 7, 2015
    Inventors: Procolo Carannante, Angelo Di Sena, Fabio Salvati, Giuseppe Ferrari, Anna Sorgente
  • Patent number: 8954649
    Abstract: A solution for managing a storage device based on a flash memory is proposed. A corresponding method starts with the step for mapping a logical memory space of the storage device (including a plurality of logical blocks) on a physical memory space of the flash memory (including a plurality of physical blocks, which are adapted to be erased individually). The physical blocks include a set of first physical blocks (corresponding to the logical blocks) and a set of second—or spare—physical blocks (for replacing each bad physical block that is unusable). The method continues by detecting each bad physical block. Each bad physical block is then discarded, so to prevent using the bad physical block for mapping the logical memory space.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: February 10, 2015
    Assignee: SK Hynix Inc.
    Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna
  • Patent number: 8924638
    Abstract: A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: December 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Procolo Carannante, Angelo Di Sena, Fabio Salvati, Giuseppe Ferrari, Anna Sorgente
  • Patent number: 8782345
    Abstract: Subject matter disclosed herein relates to sub-block accessible cache memory.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: July 15, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe Ferrari, Procolo Carannante, Angelo Di Sena, Fabio Salvati, Anna Sorgente
  • Publication number: 20130326127
    Abstract: Subject matter disclosed herein relates to sub-block accessible cache memory.
    Type: Application
    Filed: August 5, 2013
    Publication date: December 5, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Giuseppe Ferrari, Pracolo Carannante, Angelo Di Sena, Fabio Salvati, Anna Sorgente
  • Patent number: 8516194
    Abstract: Apparatus and methods for caching data are disclosed. Data is stored in a non-sub-block accessible nonvolatile memory, such as a NAND flash. A portion of the stored data is cached in a cache implemented using phase change memory using a sub-block accessible address.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: August 20, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe Ferrari, Procolo Carannante, Angelo Di Sena, Fabio Salvati, Anna Sorgente
  • Publication number: 20120304000
    Abstract: A restoring operation of a storage device based on a flash memory. In an embodiment, a storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A method may detect a plurality of conflicting physical blocks for a corrupted logical block and determines a plurality of validity indexes. One or more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block. At the end, each one of the non-selected conflicting physical blocks is discarded.
    Type: Application
    Filed: October 13, 2011
    Publication date: November 29, 2012
    Applicants: STMICROELECTRONICS PVT. LTD., STMICROELECTRONICS S.R.L.
    Inventors: Sudeep BISWAS, Angelo DI SENA, Domenico MANNA
  • Publication number: 20120131261
    Abstract: Subject matter disclosed herein relates to sub-block accessible cache memory.
    Type: Application
    Filed: November 22, 2010
    Publication date: May 24, 2012
    Applicant: Micron Technology, Inc.
    Inventors: Giuseppe Ferrari, Procolo Carannante, Angelo Di Sena, Fabio Salvati, Anna Sorgente
  • Publication number: 20120117303
    Abstract: Subject matter disclosed herein relates to storing information via a NAND flash translation layer.
    Type: Application
    Filed: November 4, 2010
    Publication date: May 10, 2012
    Applicant: Numonyx B.V.
    Inventors: Procolo Carannante, Angelo Di Sena, Fabio Salvati, Giuseppe Ferrari, Anna Sorgente
  • Patent number: 8099545
    Abstract: A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: January 17, 2012
    Assignees: STMicroelectronics S.r.l., STMicroelectronics Pvt. Ltd.
    Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna
  • Publication number: 20110289266
    Abstract: A solution for managing a storage device based on a flash memory is proposed. A corresponding method starts with the step for mapping a logical memory space of the storage device (including a plurality of logical blocks) on a physical memory space of the flash memory (including a plurality of physical blocks, which are adapted to be erased individually). The physical blocks include a set of first physical blocks (corresponding to the logical blocks) and a set of second—or spare—physical blocks (for replacing each bad physical block that is unusable). The method continues by detecting each bad physical block. Each bad physical block is then discarded, so to prevent using the bad physical block for mapping the logical memory space.
    Type: Application
    Filed: August 2, 2011
    Publication date: November 24, 2011
    Applicants: STMICROELECTRONICS PVT. LTD., STMICROELECTRONICS S.R.L.
    Inventors: SUDEEP BISWAS, ANGELO DI SENA, DOMENICO MANNA
  • Patent number: 8041883
    Abstract: A solution for restoring operation of a storage device based on a flash memory is proposed. The storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A corresponding method starts by detecting a plurality of conflicting physical blocks for a corrupted logical block (resulting from a breakdown of the storage device). The method continues by determining a plurality of validity indexes (indicative of the number of last versions of the logical sectors of the corrupted logical block that are stored in the conflicting physical blocks). One ore more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: October 18, 2011
    Assignees: STMicroelectronics S.r.l., STMicroelectronics Pvt. Ltd.
    Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna
  • Patent number: 7991942
    Abstract: A solution for managing a storage device based on a flash memory is proposed. A corresponding method starts with the step for mapping a logical memory space of the storage device (including a plurality of logical blocks) on a physical memory space of the flash memory (including a plurality of physical blocks, which are adapted to be erased individually). The physical blocks include a set of first physical blocks (corresponding to the logical blocks) and a set of second—or spare—physical blocks (for replacing each bad physical block that is unusable). The method continues by detecting each bad physical block. Each bad physical block is then discarded, so to prevent using the bad physical block for mapping the logical memory space.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: August 2, 2011
    Assignees: STMicroelectronics S.R.L., STMicroelectronics Pvt. Ltd.
    Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna
  • Publication number: 20110087832
    Abstract: A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased.
    Type: Application
    Filed: December 20, 2010
    Publication date: April 14, 2011
    Applicants: STMicroelectronics, S.r.l., STMicroelectronics Pvt. Ltd.
    Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna
  • Patent number: 7882301
    Abstract: A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: February 1, 2011
    Assignees: STMicroelectronics S.r.l., STMIcroelectronics Pvt. Ltd.
    Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna
  • Patent number: 7457909
    Abstract: A method controls write/erase operations in a memory device, such as a NAND flash memory. The method includes dividing the memory device in physical blocks, wherein each physical block is comprised of a number of pages; considering the memory device as comprising consecutive virtual blocks, each virtual block including consecutive sectors; associating to each virtual block a virtual block number; selecting the size of the virtual blocks equal to a multiple of the size of the physical blocks; and creating a virtual-to-physical mapping table having entries. Each entry in the mapping table stores a pointer to a root node of a tree structure that links logically a set of physical blocks in the memory device.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: November 25, 2008
    Inventors: Angelo Di Sena, Agata Intini
  • Publication number: 20080282023
    Abstract: A solution for restoring operation of a storage device based on a flash memory is proposed. The storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A corresponding method starts by detecting a plurality of conflicting physical blocks for a corrupted logical block (resulting from a breakdown of the storage device). The method continues by determining a plurality of validity indexes (indicative of the number of last versions of the logical sectors of the corrupted logical block that are stored in the conflicting physical blocks). One ore more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block.
    Type: Application
    Filed: May 9, 2007
    Publication date: November 13, 2008
    Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna
  • Publication number: 20080282024
    Abstract: A method of freeing physical memory space in an electrically alterable memory that includes a plurality of physical memory blocks includes a plurality of physical memory pages. Each physical memory block may be individually erased as a whole, and which memory is used to emulate a random access logical memory space including a plurality of logical memory sectors by storing updated versions of a logical memory sector data into different physical memory pages. The method includes causing a most recent version of multiple versions of logical memory sector data, stored in physical pages of at least one physical memory block, to be copied into an unused physical memory block, marking the at least one physical memory block, and when the electrically alterable memory is idle, erasing the marked physical memory block.
    Type: Application
    Filed: May 9, 2007
    Publication date: November 13, 2008
    Inventors: Sudeep Biswas, Angelo Di Sena, Domenico Manna