Patents by Inventor Anh Ly
Anh Ly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130148428Abstract: A non-volatile memory device has a charge pump for providing a programming current and an array of non-volatile memory cells. Each memory cell of the array is programmed by the programming current from the charge pump. The array of non-volatile memory cells is partitioned into a plurality of units, with each unit comprising a plurality of memory cells. An indicator memory cell is associated with each unit of non-volatile memory cells. A programming circuit programs the memory cells of each unit using the programming current, when fifty percent or less of the memory cells of each unit is to be programmed, and programs the inverse of the memory cells of each unit and the indicator memory cell associated with each unit, using the programming current, when more than fifty percent of the memory cells of each unit is to be programmed.Type: ApplicationFiled: December 8, 2011Publication date: June 13, 2013Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Thuan Vu
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Patent number: 8456904Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.Type: GrantFiled: June 29, 2011Date of Patent: June 4, 2013Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang T. Nguyen, Anh Ly, Hung Q. Nguyen
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Publication number: 20130107632Abstract: An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. A circuit that detects current flow from the second die pad is in the integrated circuit die. A switch is interposed between the first die pad and the first circuit to disconnect the first die pad from the first circuit in response to current flow detected by the circuit for detecting current flow.Type: ApplicationFiled: November 1, 2011Publication date: May 2, 2013Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
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Publication number: 20130106391Abstract: A bandgap voltage generating circuit for generating a bandgap voltage has an operational amplifier that has two inputs and an output. A current mirror circuit has at least two parallel current paths. Each of the current paths is controlled by the output from the operational amplifier. One of the current paths is coupled to one of the two inputs to the operational amplifier. A resistor divide circuit is connected to the other current path. The resistor divide circuit provides the bandgap voltage of the circuit.Type: ApplicationFiled: November 1, 2011Publication date: May 2, 2013Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
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Patent number: 8339187Abstract: Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.Type: GrantFiled: March 23, 2011Date of Patent: December 25, 2012Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang Thanh Nguyen, Nasrin Jaffari, Hung Quoc Nguyen, Anh Ly
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Patent number: 8300494Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.Type: GrantFiled: December 28, 2010Date of Patent: October 30, 2012Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang T. Nguyen, Anh Ly, Hung Q. Nguyen
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Patent number: 8270213Abstract: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.Type: GrantFiled: December 7, 2010Date of Patent: September 18, 2012Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu
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Patent number: 8232833Abstract: Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.Type: GrantFiled: May 23, 2007Date of Patent: July 31, 2012Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang Thanh Nguyen, Nasrin Jaffari, Hung Quoc Nguyen, Anh Ly
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Publication number: 20120074923Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.Type: ApplicationFiled: November 29, 2011Publication date: March 29, 2012Applicant: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang Thanh Nguyen, Anh Ly, Hung O. Nguyen, Wingfu Aaron Lau, Nasrin Jaffari, Thuan Trong Vu, Vishal Sarin, Loc B. Hoang
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Patent number: 8072815Abstract: An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.Type: GrantFiled: December 10, 2010Date of Patent: December 6, 2011Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Hung Q. Nguyen, Thuan T. Vu
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Patent number: 8067931Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.Type: GrantFiled: January 10, 2011Date of Patent: November 29, 2011Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang Thanh Nguyen, Anh Ly, Hung Q. Nguyen, Wingfu Aaron Lau, Nasrin Jaffari, Thuan Trong Vu, Vishal Sarin, Loc B. Hoang
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Publication number: 20110255346Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.Type: ApplicationFiled: June 29, 2011Publication date: October 20, 2011Applicant: Microchip Technology, Inc.Inventors: Hieu Van Tran, Sang T. Nguyen, Anh Ly, Hung Q. Nguyen
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Patent number: 8018773Abstract: An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.Type: GrantFiled: March 4, 2009Date of Patent: September 13, 2011Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Hung Q. Nguyen, Thuan T. Vu
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Patent number: 8010638Abstract: A method and apparatus updates software data for an interface unit that interfaces a portable audio/video player with another audio/video system. When the portable audio/video players are updated by adding new features, etc., the method and apparatus enables the users to obtain the corresponding update file for the interface unit in the same manner that the user obtains the music file. Thus, the user can easily and quickly obtain the update file for updating the interface unit and store it in the portable audio/video player in the same manner as the music files. For executing the update operation, the user selects the update file from the play list and starts playing the update file on the portable audio/video player while connecting it to the interface unit.Type: GrantFiled: October 4, 2007Date of Patent: August 30, 2011Assignee: Alpine Electronics, Inc.Inventors: Luis Stohr, Ben Khau, Satoshi Tanimoto, Anh Ly
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Patent number: 7990773Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.Type: GrantFiled: November 20, 2009Date of Patent: August 2, 2011Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang T. Nguyen, Anh Ly, Hung Q. Nguyen
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Publication number: 20110169558Abstract: Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.Type: ApplicationFiled: March 23, 2011Publication date: July 14, 2011Applicant: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang Thanh Nguyen, Nasrin Jaffari, Hung Quoc Nguyen, Anh Ly
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Patent number: 7969239Abstract: A novel capacitor for use in a charge pump circuit has a substrate with a planar surface. A first electrode is in a first plane spaced apart from the planar surface. A second electrode is adjacent to and is spaced apart from the first electrode in the first plane and is capacitively coupled thereto. A third electrode is in a second plane, spaced apart from the first plane and is capacitively coupled to the first electrode. A fourth electrode is adjacent to and spaced apart from the third electrode in the second plane and is capacitively coupled to the third electrode and capacitively coupled to the second electrode. The first and fourth electrodes are electrically connected together and the second and third electrodes are electrically connected together. In addition, a cylindrical shape electrode, and a great wall electrode, and charge pump capacitor-by-pattern-filling is disclosed.Type: GrantFiled: September 29, 2009Date of Patent: June 28, 2011Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Q. Nguyen, Thuan T. Vu, Anh Ly
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Publication number: 20110121799Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.Type: ApplicationFiled: January 10, 2011Publication date: May 26, 2011Applicant: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang Thanh Nguyen, Anh Ly, Hung Q. Nguyen, Wingfu Aaron Lau, Nasrin Jaffari, Thuan Trong Vu, Vishal Sarin, Loc B. Hoang
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Publication number: 20110122693Abstract: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.Type: ApplicationFiled: December 7, 2010Publication date: May 26, 2011Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu
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Patent number: 7939892Abstract: A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.Type: GrantFiled: October 6, 2010Date of Patent: May 10, 2011Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Sang Thanh Nguyen, Vishal Sarin, Hung Q. Nguyen, William John Saiki, Loc B. Hoang