Patents by Inventor Anh Ly

Anh Ly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CURRENT COMPENSATION BLOCK AND METHOD FOR PROGRAMMING ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20200051636
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.
    Type: Application
    Filed: August 25, 2019
    Publication date: February 13, 2020
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • Redundant Memory Access For Rows Or Columns Containing Faulty Memory Cells In Analog Neural Memory In Deep Learning Artificial Neural Network
    Publication number: 20200019849
    Abstract: Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.
    Type: Application
    Filed: October 3, 2018
    Publication date: January 16, 2020
    Inventors: Hieu Van Tran, Stanley Hong, Thuan Vu, Anh Ly, Hien Pham, Kha Nguyen, Han Tran
  • Method and apparatus for high voltage generation for analog neural memory in deep learning artificial neural network
    Patent number: 10522226
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: December 31, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • METHOD AND APPARATUS FOR HIGH VOLTAGE GENERATION FOR ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20190341110
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.
    Type: Application
    Filed: July 23, 2018
    Publication date: November 7, 2019
    Inventors: Hieu Van Tran, Thuan Vu, Staniey Hong, Anh Ly, Vlpln Tlwarl, Nhan Do
  • Dynamic programming of advanced nanometer flash memory
    Patent number: 10460810
    Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 29, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
  • Decoders For Analog Neural Memory In Deep Learning Artificial Neural Network
    Publication number: 20190286976
    Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.
    Type: Application
    Filed: May 29, 2018
    Publication date: September 19, 2019
    Inventors: Hieu Van Tran, Stanley Hong, Anh Ly, Thuan Vu, Hien Pham, Kha Nguyen, Han TRan
  • Method And Apparatus For Configuring Array Columns And Rows For Accessing Flash Memory Cells
    Publication number: 20190272876
    Abstract: A non-volatile memory device is disclosed. The non-volatile memory device comprises an array of flash memory cells comprising a plurality of flash memory cells organized into rows and columns, wherein the array is further organized into a plurality of sectors, each sector comprising a plurality of rows of flash memory cells, and a row driver selectively coupled to a first row and a second row.
    Type: Application
    Filed: May 20, 2019
    Publication date: September 5, 2019
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Vipin Tiwari, Nhan Do
  • Programmable Neuron For Analog Non-Volatile Memory In Deep Learning Artificial Neural Network
    Publication number: 20190205729
    Abstract: Numerous embodiments for processing the current output of a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The embodiments comprise a summer circuit and an activation function circuit. The summer circuit and/or the activation function circuit comprise circuit elements that can be adjusted in response to the total possible current received from the VMM to optimize power consumption.
    Type: Application
    Filed: March 27, 2018
    Publication date: July 4, 2019
    Inventors: Hieu Van Tran, Stanley Hong, Anh Ly, Thuan Vu, Hien Pham, Kha Nguyen, Han Tran
  • Method and apparatus for configuring array columns and rows for accessing flash memory cells
    Patent number: 10340010
    Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: July 2, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Vipin Tiwari, Nhan Do
  • Flash memory system using negative high voltage level shifter
    Patent number: 10325666
    Abstract: During a program, read, or erase operation of one or more non-volatile flash memory cells in an array of non-volatile flash memory cells, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected non-volatile flash memory cells. The negative voltage is generated by a negative high voltage level shifter using one of several embodiments disclosed herein.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: June 18, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
  • Sensing amplifier comprising fully depleted silicon-on-insulator transistors for reading a selected flash memory cell in an array of flash memory cells
    Patent number: 10297327
    Abstract: The present invention relates to a flash memory system comprising one or more sense amplifiers for reading data stored in flash memory cells. The sense amplifiers utilize fully depleted silicon-on-insulator transistors to minimize leakage. The fully depleted silicon-on-insulator transistors comprise one or more fully depleted silicon-on-insulator NMOS transistors and/or one or more fully depleted silicon-on-insulator PMOS transistors.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: May 21, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
  • High speed sensing for advanced nanometer flash memory device
    Patent number: 10283206
    Abstract: Improved flash memory sensing circuits are disclosed. In one embodiment, a sensing circuit comprises a memory data read block, a memory reference block, a differential amplifier, and a precharge circuit. The precharge circuit compensates for parasitic capacitance between a bit line coupled to a selected memory cell and adjacent bit lines.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: May 7, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen, Vipin Tiwari
  • Method and apparatus for configuring array columns and rows for accessing flash memory cells
    Patent number: 10269432
    Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: April 23, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Vipin Tiwari, Nhan Do
  • Flash Memory System Using Negative High Voltage Level Shifter
    Publication number: 20190115088
    Abstract: During a program, read, or erase operation of one or more non-volatile flash memory cells in an array of non-volatile flash memory cells, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected non-volatile flash memory cells. The negative voltage is generated by a negative high voltage level shifter using one of several embodiments disclosed herein.
    Type: Application
    Filed: December 12, 2018
    Publication date: April 18, 2019
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
  • Sensing amplifier comprising bias circuitry coupled to bit line and dummy bitline for performing read operation in flash memory devices
    Patent number: 10236068
    Abstract: The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: March 19, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu
  • Methods For Writing To An Array Of Resistive Random Access Memory Cells
    Publication number: 20190080754
    Abstract: Numerous embodiments of methods for writing to a resistive random access memory (RRAM) cell are disclosed. In one embodiment, the system verifies if a current through the RRAM cell exceeds a threshold value, and if it does not, the system executes a concurrent write-while-verify operation. In another embodiment, the system verifies if current through the RRAM cell has reached a target value, and if it has not, the system executes a write operation and then verifies the write operation using a current comparison.
    Type: Application
    Filed: August 31, 2018
    Publication date: March 14, 2019
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Stanley Hong, Feng Zhou, Xian Liu, Nhan Do
  • Architectures and Layouts for an Array Of Resistive Random Access Memory Cells and Read and Write Methods Thereof
    Publication number: 20190080753
    Abstract: Various architectures and layouts for an array of resistive random access memory (RRAM) cells are disclosed. The RRAM cells are organized into rows and columns, with each cell comprising a top electrode, a bottom electrode, and a switching layer. Circuitry is included for improving the reading and writing of the array, including the addition of a plurality of columns of dummy RRAM cells in the array used as a ground source, connecting source lines to multiple pairs of rows of RRAM cells, and the addition of rows of isolation transistors.
    Type: Application
    Filed: September 11, 2017
    Publication date: March 14, 2019
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Stanley Hong, Feng Zhou, Xian Liu, Nhan Do
  • Sense Amplifier Circuit For Reading Data In A Flash Memory Cell
    Publication number: 20190066805
    Abstract: Numerous embodiments for an improved sense amplifier circuit for reading data in a flash memory cell are disclosed. The embodiments each compare current or voltage measurements from a data block with a reference block to determine the value stored in the selected memory cell in the data block. The use of one or more localized boost circuits allow the embodiments to utilize lower operating voltages than prior art sense amplifier circuits, resulting in reduced power consumption.
    Type: Application
    Filed: August 25, 2017
    Publication date: February 28, 2019
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Stanley Hong
  • Power sequencing for embedded flash memory devices
    Patent number: 10216242
    Abstract: A system and method for improved power sequencing within an embedded flash memory device is disclosed. Various power-on sequences and power-down sequences for a plurality of voltage sources are utilized to improve the performance of an embedded flash memory device. The plurality of voltage sources can be used for different purposes within the embedded flash memory device.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: February 26, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Anh Ly, Hung Quoc Nguyen
  • Sense amplifier circuit for reading data in a flash memory cell
    Patent number: 10199112
    Abstract: Numerous embodiments for an improved sense amplifier circuit for reading data in a flash memory cell are disclosed. The embodiments each compare current or voltage measurements from a data block with a reference block to determine the value stored in the selected memory cell in the data block. The use of one or more localized boost circuits allow the embodiments to utilize lower operating voltages than prior art sense amplifier circuits, resulting in reduced power consumption.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: February 5, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Stanley Hong