Abstract: A system and method for low latency switching of data packets in a network switch. A network switch may include multiple input ports, multiple output ports, and a shared random access memory coupled to the input ports and output ports by data transport logic. Under normal operation, the data transport logic stores packet data into the memory. Later, the packet data is read from the memory and output to a destination output port. To reduce latency when the switch is not congested, the switching logic may be configured to perform a cut-through operation by routing packets directly from input ports to output ports without storing any portion of the packet in the memory. Alternatively, the switch may begin forwarding the stored packet data to the output port before the entire packet has been received or stored in the memory.

Abstract: A peptide of relative molecular mass less than 6500 comprising at least ten consecutive amino acid residues surrounding the phenylalanine (508), or at least ten consecutive residues including a portion of the region between residues (508 and 551), in the polypeptide sequence of human cystic fibrosis transmembrane regulator (CFTR), or a variant or precursor thereof. A peptide as defined above having between 12 and 50 amino acid residues. Methods of treating cystic fibrosis are also disclosed. A method of classifying a disease state associated with epithelial cell dysfunction in a patient is disclosed. The method includes obtaining a suitable epithelial cell sample from the patient and determining for one or more of the following whether the measured parameter is altered compared to a control epithelial cell, the measured parameters being: (i) nucleoside diphosphate kinase (NDPK) function, (ii) phosphorylation of annexin, (iii) phosphorylation of other membrane proteins, and (iv) ATPase activity.

Abstract: A processor includes a system bus interface that permits short set-up and hold times for bus signals including loop-back signals. Loop-back signals are transferred from an input cell in the interface to a target I/O cell in the interface without resynchronizing the loop-back signal with the processor clock. Accordingly, set-up and hold times for the loop-back signal need only be sufficient to allow for jitter or uncompensated delay in the bus clock signal at the target I/O cell. The processing core provides valid signals that might be required for generating an output signal from the target cell. The core avoids changing those signals near triggering edges of the bus clock signal to prevent the signals from changing before the target I/O cell uses the required signals. Typically, the loop-back signal determines whether I/O cell is enabled for output and is also used at the edge of the bus clock signal.

Abstract: A processor includes a processing core that is operable at a frequency that is an odd half-integer multiple of a bus clock frequency. Signals on a system bus are synchronized with a selected edge, e.g., the rising edge, of a bus clock signal, but the processing core requires signals synchronized with a processor clock signal. Signal crossing between the clock domain of the processing core and the clock domain of the system bus pass through a storage element that selectably latches a value of the signal either at a rising edge or a falling edge of the processor clock signal. A control circuit selects either rising-edge or falling-edge latching depending on which edge (rising or falling) is closest to being synchronized with the selected edge of the bus clock signal.